| //Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp |
| // Spec Reference: dsp32shift vmax / vmax |
| # mach: bfin |
| |
| .include "testutils.inc" |
| start |
| |
| |
| |
| imm32 r0, 0x11002001; |
| imm32 r1, 0x12001001; |
| imm32 r2, 0x11301302; |
| imm32 r3, 0x43001003; |
| imm32 r4, 0x11601604; |
| imm32 r5, 0x71001705; |
| imm32 r6, 0x81008006; |
| imm32 r7, 0x1900b007; |
| A0 = R3; |
| R1 = VIT_MAX( R1 , R0 ) (ASL); |
| R2 = VIT_MAX( R2 , R1 ) (ASL); |
| R3 = VIT_MAX( R3 , R2 ) (ASL); |
| R4 = VIT_MAX( R4 , R3 ) (ASL); |
| R5 = VIT_MAX( R5 , R4 ) (ASL); |
| R6 = VIT_MAX( R6 , R5 ) (ASL); |
| R7 = VIT_MAX( R7 , R6 ) (ASL); |
| R0 = VIT_MAX( R0 , R7 ) (ASL); |
| CHECKREG r0, 0x20018100; |
| CHECKREG r1, 0x12002001; |
| CHECKREG r2, 0x13022001; |
| CHECKREG r3, 0x43002001; |
| CHECKREG r4, 0x16044300; |
| CHECKREG r5, 0x71004300; |
| CHECKREG r6, 0x81007100; |
| CHECKREG r7, 0x19008100; |
| |
| imm32 r0, 0x11002001; |
| imm32 r1, 0xd2001001; |
| imm32 r2, 0x14301302; |
| imm32 r3, 0x43001003; |
| imm32 r4, 0x11f01604; |
| imm32 r5, 0xb1001705; |
| imm32 r6, 0xd1008006; |
| imm32 r7, 0x39056707; |
| R1 = VIT_MAX( R1 , R3 ) (ASL); |
| R2 = VIT_MAX( R2 , R4 ) (ASL); |
| R3 = VIT_MAX( R3 , R6 ) (ASL); |
| R4 = VIT_MAX( R4 , R5 ) (ASL); |
| R5 = VIT_MAX( R5 , R7 ) (ASL); |
| R6 = VIT_MAX( R6 , R0 ) (ASL); |
| R7 = VIT_MAX( R7 , R1 ) (ASL); |
| R0 = VIT_MAX( R0 , R2 ) (ASL); |
| CHECKREG r0, 0x20011604; |
| CHECKREG r1, 0x10014300; |
| CHECKREG r2, 0x14301604; |
| CHECKREG r3, 0x4300D100; |
| CHECKREG r4, 0x16041705; |
| CHECKREG r5, 0x17056707; |
| CHECKREG r6, 0xD1002001; |
| CHECKREG r7, 0x67074300; |
| |
| imm32 r0, 0xa1011001; |
| imm32 r1, 0x1b002001; |
| imm32 r2, 0x81c01302; |
| imm32 r3, 0x910d1403; |
| imm32 r4, 0x2100e504; |
| imm32 r5, 0x31007f65; |
| imm32 r6, 0x41007006; |
| imm32 r7, 0x15001801; |
| R1 = VIT_MAX( R1 , R0 ) (ASR); |
| R2 = VIT_MAX( R2 , R1 ) (ASR); |
| R3 = VIT_MAX( R3 , R2 ) (ASR); |
| R4 = VIT_MAX( R4 , R3 ) (ASR); |
| R5 = VIT_MAX( R5 , R4 ) (ASR); |
| R6 = VIT_MAX( R6 , R5 ) (ASR); |
| R7 = VIT_MAX( R7 , R6 ) (ASR); |
| R0 = VIT_MAX( R0 , R7 ) (ASR); |
| CHECKREG r0, 0x1001910D; |
| CHECKREG r1, 0x20011001; |
| CHECKREG r2, 0x81C02001; |
| CHECKREG r3, 0x910D81C0; |
| CHECKREG r4, 0x2100910D; |
| CHECKREG r5, 0x7F65910D; |
| CHECKREG r6, 0x7006910D; |
| CHECKREG r7, 0x1801910D; |
| |
| imm32 r0, 0xe1011001; |
| imm32 r1, 0x4b002001; |
| imm32 r2, 0x8fc01302; |
| imm32 r3, 0x910d1403; |
| imm32 r4, 0xb100e504; |
| imm32 r5, 0x41007f65; |
| imm32 r6, 0xaf007006; |
| imm32 r7, 0x16001801; |
| R0 = VIT_MAX( R4 , R0 ) (ASR); |
| R1 = VIT_MAX( R5 , R1 ) (ASR); |
| R2 = VIT_MAX( R6 , R2 ) (ASR); |
| R3 = VIT_MAX( R7 , R3 ) (ASR); |
| R4 = VIT_MAX( R0 , R4 ) (ASR); |
| R5 = VIT_MAX( R1 , R5 ) (ASR); |
| R6 = VIT_MAX( R2 , R6 ) (ASR); |
| R7 = VIT_MAX( R3 , R7 ) (ASR); |
| CHECKREG r0, 0xE5041001; |
| CHECKREG r1, 0x7F654B00; |
| CHECKREG r2, 0xAF008FC0; |
| CHECKREG r3, 0x1801910D; |
| CHECKREG r4, 0x1001E504; |
| CHECKREG r5, 0x7F657F65; |
| CHECKREG r6, 0xAF00AF00; |
| CHECKREG r7, 0x910D1801; |
| |
| |
| |
| pass |