)]}'
{
  "commit": "fa88a361f99ecfddce4cc7228932ccc35879a6e8",
  "tree": "37239d85026e8de195943163c45e3028b7cba86b",
  "parents": [
    "15aacf324fb871871e2162ea8769a9f82c043909"
  ],
  "author": {
    "name": "Haochen Jiang",
    "email": "haochen.jiang@intel.com",
    "time": "Tue Dec 19 16:35:00 2023 +0800"
  },
  "committer": {
    "name": "Haochen Jiang",
    "email": "haochen.jiang@intel.com",
    "time": "Tue Dec 19 16:35:24 2023 +0800"
  },
  "message": "x86: Remove the restriction for size of the mask register in AVX10\n\nSince AVX10.1/256 will also allow 64 bit mask register, we will\nremove the restriction for size of the mask register in AVX10.\n\ngas/ChangeLog:\n\n\t* config/tc-i386.c (VSZ128, VSZ256, VSZ512): New.\n\t(VEX_check_encoding): Remove opcode_modifier check for vsz.\n\t* testsuite/gas/i386/avx10-vsz.l: Remove testcases for mask\n\tregisters since they are not needed.\n\t* testsuite/gas/i386/avx10-vsz.s: Ditto.\n\nopcodes/ChangeLog:\n\n\t* i386-gen.c: Remove Vsz.\n\t* i386-opc.h: Ditto.\n\t* i386-opc.tbl: Remove kvsz.\n\t* i386-tbl.h: Regenerated.\n",
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