sim/d30v/Makefile.in

#   Mitsubishi Electric Corp. D30V Simulator.
#   Copyright (C) 1997, Free Software Foundation, Inc.
#   Contributed by Cygnus Support.
# 
# This file is part of GDB, the GNU debugger.
# 
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
# 
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
# 
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

M4= @M4@


## COMMON_PRE_CONFIG_FRAG

# These variables are given default values in COMMON_PRE_CONFIG_FRAG.
# We override the ones we need to here.
# Not all of these need to be mentioned, only the necessary ones.

# List of object files, less common parts.
SIM_OBJS = \
	$(SIM_NEW_COMMON_OBJS) \
	engine.o cpu.o \
	s_support.o l_support.o \
	s_idecode.o l_idecode.o  \
	s_semantics.o l_semantics.o \
	sim-calls.o itable.o \
	sim-hload.o \
	sim-hrw.o \
	sim-engine.o \
	sim-stop.o \
	sim-reason.o \
	sim-resume.o

# List of extra dependencies.
# Generally this consists of simulator specific files included by sim-main.h.
SIM_EXTRA_DEPS = itable.h s_idecode.h l_idecode.h cpu.h alu.h

# List of generators
SIM_GEN=tmp-igen

# List of extra flags to always pass to $(CC).
SIM_EXTRA_CFLAGS = @sim_trapdump@

# List of main object files for `run'.
SIM_RUN_OBJS = nrun.o

# Dependency of `clean' to clean any extra files.
SIM_EXTRA_CLEAN = clean-igen

# This selects the d30v newlib/libgloss syscall definitions.
NL_TARGET=-DNL_TARGET_d30v

## COMMON_POST_CONFIG_FRAG

MAIN_INCLUDE_DEPS = tconfig.h
INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS)

# Rules need to build $(SIM_OBJS), plus whatever else the target wants.

# ... target specific rules ...

# Filter to eliminate known warnings
FILTER = 2>&1 | egrep -v "Discarding instruction|instruction field of type \`compute\' changed to \`cache\'|Instruction format is not 64 bits wide"

BUILT_SRC_FROM_IGEN = \
	s_icache.h \
	s_icache.c \
	s_idecode.h \
	s_idecode.c \
	s_semantics.h \
	s_semantics.c \
	s_model.h \
	s_model.c \
	s_support.h \
	s_support.c \
	l_icache.h \
	l_icache.c \
	l_idecode.h \
	l_idecode.c \
	l_semantics.h \
	l_semantics.c \
	l_model.h \
	l_model.c \
	l_support.h \
	l_support.c \
	itable.h itable.c
$(BUILT_SRC_FROM_IGEN): tmp-igen
#

.PHONY: clean-igen
clean-igen:
	rm -f $(BUILT_SRC_FROM_IGEN)
	rm -f tmp-igen tmp-insns

../igen/igen:
	cd ../igen && $(MAKE)

tmp-igen: $(srcdir)/dc-short $(srcdir)/d30v-insns $(srcdir)/ic-d30v ../igen/igen
	cd ../igen && $(MAKE)
	echo "# 1 \"$(srcdir)/d30v-insns\"" > tmp-insns
	$(M4) < $(srcdir)/d30v-insns >> tmp-insns 
	@echo "Generating short version ..."
	../igen/igen \
		-G gen-zero-r0 \
		-G direct-access \
		-G default-nia-minus-one \
		-G conditional-issue \
		-G verify-slot \
		-G field-widths \
		-F short,emul \
		-B 32 \
		-P "s_" \
		-o $(srcdir)/dc-short \
		-k $(srcdir)/ic-d30v \
		-n $(srcdir)/d30v-insns -i tmp-insns \
		-n s_icache.h    -hc tmp-icache.h \
		-n s_icache.c    -c  tmp-icache.c \
		-n s_semantics.h -hs tmp-semantics.h \
		-n s_semantics.c -s  tmp-semantics.c \
		-n s_idecode.h   -hd tmp-idecode.h \
		-n s_idecode.c   -d  tmp-idecode.c \
		-n s_model.h     -hm tmp-model.h \
		-n s_model.c     -m  tmp-model.c \
		-n s_support.h   -hf tmp-support.h \
		-n s_support.c   -f  tmp-support.c $(FILTER)
	$(srcdir)/../../move-if-change tmp-icache.h s_icache.h
	$(srcdir)/../../move-if-change tmp-icache.c s_icache.c
	$(srcdir)/../../move-if-change tmp-idecode.h s_idecode.h
	$(srcdir)/../../move-if-change tmp-idecode.c s_idecode.c
	$(srcdir)/../../move-if-change tmp-semantics.h s_semantics.h
	$(srcdir)/../../move-if-change tmp-semantics.c s_semantics.c
	$(srcdir)/../../move-if-change tmp-model.h s_model.h
	$(srcdir)/../../move-if-change tmp-model.c s_model.c
	$(srcdir)/../../move-if-change tmp-support.h s_support.h
	$(srcdir)/../../move-if-change tmp-support.c s_support.c
	@echo "Generating long version ..."
	../igen/igen \
		-G gen-zero-r0 \
		-G direct-access \
		-G default-nia-minus-one \
		-G conditional-issue \
		-G field-widths \
		-F long,emul \
		-B 64 \
		-P "l_" \
		-o $(srcdir)/dc-short \
		-k $(srcdir)/ic-d30v \
		-i tmp-insns \
		-n l_icache.h    -hc tmp-icache.h \
		-n l_icache.c    -c  tmp-icache.c \
		-n l_semantics.h -hs tmp-semantics.h \
		-n l_semantics.c -s  tmp-semantics.c \
		-n l_idecode.h   -hd tmp-idecode.h \
		-n l_idecode.c   -d  tmp-idecode.c \
		-n l_model.h     -hm tmp-model.h \
		-n l_model.c     -m  tmp-model.c \
		-n l_support.h   -hf tmp-support.h \
		-n l_support.c   -f  tmp-support.c $(FILTER)
	$(srcdir)/../../move-if-change tmp-icache.h l_icache.h
	$(srcdir)/../../move-if-change tmp-icache.c l_icache.c
	$(srcdir)/../../move-if-change tmp-idecode.h l_idecode.h
	$(srcdir)/../../move-if-change tmp-idecode.c l_idecode.c
	$(srcdir)/../../move-if-change tmp-semantics.h l_semantics.h
	$(srcdir)/../../move-if-change tmp-semantics.c l_semantics.c
	$(srcdir)/../../move-if-change tmp-model.h l_model.h
	$(srcdir)/../../move-if-change tmp-model.c l_model.c
	$(srcdir)/../../move-if-change tmp-support.h l_support.h
	$(srcdir)/../../move-if-change tmp-support.c l_support.c
	@echo "Generating instruction database ..."
	../igen/igen \
		-G field-widths \
		-F short,long,emul \
		-B 64 \
		-o $(srcdir)/dc-short \
		-k $(srcdir)/ic-d30v \
		-i tmp-insns \
		-n itable.h    -ht tmp-itable.h \
		-n itable.c    -t  tmp-itable.c $(FILTER)
	$(srcdir)/../../move-if-change tmp-itable.h itable.h
	$(srcdir)/../../move-if-change tmp-itable.c itable.c
	touch tmp-igen

ENGINE_H = \
	sim-main.h \
	$(srcdir)/../common/sim-basics.h \
	config.h \
	$(srcdir)/../common/sim-config.h \
	$(srcdir)/../common/sim-inline.h \
	$(srcdir)/../common/sim-types.h \
	$(srcdir)/../common/sim-bits.h \
	$(srcdir)/../common/sim-endian.h \
	itable.h \
	l_idecode.h s_idecode.h \
	cpu.h \
	alu.h \
	$(srcdir)/../common/sim-alu.h \
	$(srcdir)/../common/sim-core.h \
	$(srcdir)/../common/sim-events.h \

engine.o: engine.c $(ENGINE_H)
sim-calls.o: sim-calls.c $(ENGINE_H) $(srcdir)/../common/sim-utils.h $(srcdir)/../common/sim-options.h
cpu.o: cpu.c $(ENGINE_H)
s_support.o: s_support.c $(ENGINE_H)
l_support.o: l_support.c $(ENGINE_H)
s_semantics.o: s_semantics.c $(ENGINE_H)
l_semantics.o: l_semantics.c $(ENGINE_H)