sim/sh: check PFSCR.PR setting for fldi0 and fldi1 insns

On SH variants with double-precision FPU the insns fli0 and flid1 are only
defined when FPSCR.PR = 0.  The hardware does not necessarily trap but might
quietly load undefined values.  However, qemu traps in that case, so do the
same.

sim/sh/gencode.c

diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c
index 42009fc..9c882d2 100644
--- a/sim/sh/gencode.c
+++ b/sim/sh/gencode.c
@@ -645,16 +645,20 @@
   /* sh2e */
   { "", "", "fldi0 <FREG_N>", "1111nnnn10001101",
     {
-      "SET_FR (n, (float) 0.0);",
-      "/* FIXME: check for DP and (n & 1) == 0?  */",
+      "if (FPSCR_PR)",
+      "  RAISE_EXCEPTION (SIGILL);",
+      "else",
+      "  SET_FR (n, (float) 0.0);",
     },
   },
 
   /* sh2e */
   { "", "", "fldi1 <FREG_N>", "1111nnnn10011101",
     {
-      "SET_FR (n, (float) 1.0);",
-      "/* FIXME: check for DP and (n & 1) == 0?  */",
+      "if (FPSCR_PR)",
+      "  RAISE_EXCEPTION (SIGILL);",
+      "else",
+      "  SET_FR (n, (float) 1.0);",
     },
   },