)]}'
{
  "commit": "19b58b26585b296ce0e506333e17a49dd2acf4c5",
  "tree": "07758f4c25eb75959935304475e70bba004e8917",
  "parents": [
    "77dd5c805f4347c5de657ddeed032a2e9bd7abc7"
  ],
  "author": {
    "name": "Nelson Chu",
    "email": "nelson.chu@sifive.com",
    "time": "Mon Sep 27 01:29:58 2021 -0700"
  },
  "committer": {
    "name": "Nelson Chu",
    "email": "nelson.chu@sifive.com",
    "time": "Thu Oct 28 08:52:25 2021 +0800"
  },
  "message": "RISC-V/SiFive: Added SiFive custom cache control instructions.\n\nAccording to the chapter 10 of the following U74-MC manual,\nhttps://sifive.cdn.prismic.io/sifive/6d9a2510-2632-44f3-adb9-d0430f139372_sifive_coreip_U74MC_AXI4_rtl_v19_08p2p0_release_manual.pdf\n\nand the implementations of freedom-metal,\nhttps://github.com/sifive/freedom-metal/blob/v201908-branch/src/cache.c\n\n* Encodings,\n31-25   24-20 19-15 14-12  11-7  6-0\nFUNCT7  RS2   RS1   FUNCT3 RD    OPCODE\n1111110 00000 xxxxx 000    00000 1110011 CFLUSH.D.L1\n1111110 00010 xxxxx 000    00000 1110011 CDISCARD.D.L1\n1111110 00001 00000 000    00000 1110011 CFLUSH.I.L1\n\n* Extension names,\nxsfcflushdlone:   CFLUSH.D.L1.\nxsfcdiscarddlone: CDISCARD.D.L1.\nxsfcflushilone:   CFLUSH.I.L1.\n\n* Vendor target triples,\nFor assembler, the target vendor is defined as TARGET_VENDOR in the\ngas/config.h, but I don\u0027t see any related settings in bfd/config.h\nand opcode/config.  Since we may have vendor relocations in the future,\nand these relocation numbers may repeat, I add a new RISCV_TARGET_VENDOR\nin the bfd/config.h for riscv.  The vendor name will be stored in the\nbfd/cpu-riscv.c, so that all tools (gas, bfd, opcode, ...) can get\nthe vendor name from the configure setting.\n\nIf the --with-arch configure option, -march gas option and elf architecture\nattributes are not set, then we will generate the default ISA string\naccording to the chosen target vendor.  For example, if you build the\nbinutils with the configure option, --target\u003driscv64-sifive-elf, then\nthe assembler will find the whole supported extension tables in the\nbfd/elfxx-riscv.c, and generate the suitable ISA string.\n\nbfd/\n\t* configure.ac (RISCV_TARGET_VENDOR): Defined to store target_vendor,\n\tonly when the target is riscv*.\n\t* config.in: Regenerated.\n\t* configure: Regenerated.\n\t* cpu-riscv.c (riscv_vendor_name): Defined to RISCV_TARGET_VENDOR.\n\t* cpu-riscv.h (enum riscv_spec_class): Added VENDOR_SPEC_CLASS_SIFIVE.\n\t* elfxx-riscv. (EXT_SIFIVE): Defined to choose the default extensions\n\tfor sifive.\n\t(riscv_supported_vendor_sifive_ext): Added extensions for sifive cache\n\tcontrol instructions.\n\t(riscv_supported_std_ext, riscv_all_supported_ext): Updated.\n\t(riscv_get_default_ext_version): Updated.\n\t(riscv_set_default_arch): Updated.\ngas/\n\t* config/tc-riscv.c (VENDOR_SIFIVE_EXT): Added.\n\t(riscv_extended_subset_supports): Handle INSN_CLASS_XSF*.\n\t(op_vendor_sifive_hash): Added to store sifive opcodes.\n\t(md_begin): Init the op_vendor_sifive_hash.\n\t(riscv_find_extended_opcode_hash): Find the opcodes from\n\top_vendor_sifive_hash.\n\t* testsuite/gas/riscv/extended/sifive-insns.d: New testcase.\n\t* testsuite/gas/riscv/extended/sifive-insns.s: Likewise.\ninclude/\n\t* opcode/riscv-opc-extended.h: Added opcodes for sifive cache\n\tinstructions.\n\t* opcode/riscv.h (enum riscv_extended_insn_class): Added INSN_CLASS_XSF*.\nopcodes/\n\t* riscv-opc.c (riscv_vendor_sifive_opcodes): Added.\n\t(riscv_extended_opcodes): Updated.\n",
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