blob: f682c40acd97d7bd952238d987edd8b099ff1ddd [file] [log] [blame]
# Copyright (C) 2017-2021 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
# Test the new DW_OP_LLVM_extend operation.
#
# The test uses a composite location description, where all the pieces
# are allocated in the same register by using the new operation.
load_lib dwarf.exp
# This test can only be run on targets which support DWARF-2 and use gas.
if {![dwarf2_support]} {
return 0
}
# Choose suitable integer registers for the test.
set dwarf_regnum 0
if { [is_aarch64_target] } {
set regname x0
} elseif { [is_aarch32_target]
|| [istarget "s390*-*-*" ]
|| [istarget "powerpc*-*-*"]
|| [istarget "rs6000*-*-aix*"] } {
set regname r0
} elseif { [is_x86_like_target] } {
set regname eax
} elseif { [is_amd64_regs_target] } {
set regname rax
} else {
verbose "Skipping ${gdb_test_file_name}."
return
}
standard_testfile var-access.c ${gdb_test_file_name}-dw.S
# Make some DWARF for the test.
set asm_file [standard_output_file $srcfile2]
Dwarf::assemble $asm_file {
global dwarf_regnum regname srcdir subdir srcfile
set buf_src [gdb_target_symbol buf]
set main_result [function_range main ${srcdir}/${subdir}/${srcfile}]
set main_start [lindex $main_result 0]
set main_length [lindex $main_result 1]
cu {} {
DW_TAG_compile_unit {
{DW_AT_name var-access.c}
{DW_AT_comp_dir /tmp}
} {
declare_labels int_type_label char_type_label array_type_label
# define char type
char_type_label: DW_TAG_base_type {
{DW_AT_name "char"}
{DW_AT_encoding @DW_ATE_signed}
{DW_AT_byte_size 1 DW_FORM_sdata}
}
int_type_label: DW_TAG_base_type {
{DW_AT_name "int"}
{DW_AT_encoding @DW_ATE_signed}
{DW_AT_byte_size 4 DW_FORM_sdata}
}
array_type_label: DW_TAG_array_type {
{DW_AT_type :$char_type_label}
} {
DW_TAG_subrange_type {
{DW_AT_type :$int_type_label}
{DW_AT_upper_bound 7 DW_FORM_udata}
}
}
DW_TAG_subprogram {
{DW_AT_name main}
{DW_AT_low_pc $main_start addr}
{DW_AT_high_pc $main_length data8}
} {
# All array elements are in first byte of REGNAME register.
DW_TAG_variable {
{DW_AT_name var_array_1}
{DW_AT_type :$array_type_label}
{DW_AT_location {
DW_OP_regx $dwarf_regnum
DW_OP_LLVM_extend 8 8
} SPECIAL_expr}
}
# All array elements are in fourth byte of REGNAME register.
DW_TAG_variable {
{DW_AT_name var_array_2}
{DW_AT_type :$array_type_label}
{DW_AT_location {
DW_OP_regx $dwarf_regnum
DW_OP_LLVM_offset_constu 3
DW_OP_LLVM_extend 8 8
} SPECIAL_expr}
}
}
}
}
}
if { [prepare_for_testing ${testfile}.exp ${testfile} \
[list $srcfile $asm_file] {nodebug}] } {
return -1
}
if ![runto_main] {
return -1
}
gdb_test_no_output "set var \$$regname = 0x04030201" "init reg"
# Determine byte order.
set endian [get_endianness]
switch $endian {
little {set val "0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1"}
big {set val "0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4"}
}
gdb_test "print/x var_array_1" " = \\{${val}\\}" "var_array_1 print"
switch $endian {
little {set val "0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4"}
big {set val "0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1"}
}
gdb_test "print/x var_array_2" " = \\{${val}\\}" "var_array_2 print"