blob: f783d41ba3d05dc56b829ac873b27bc82f2cd1f6 [file] [log] [blame]
# fr30 testcase for asr $Rj,$Ri, asr $u4,$Rj
# mach(): fr30
.include "testutils.inc"
START
.text
.global asr
asr:
; Test asr $Rj,$Ri
mvi_h_gr 0xdeadbee0,r7 ; Shift by 0
mvi_h_gr 0x80000000,r8
set_cc 0x05 ; Set mask opposite of expected
asr r7,r8
test_cc 1 0 0 0
test_h_gr 0x80000000,r8
mvi_h_gr 0xdeadbee1,r7 ; Shift by 1
mvi_h_gr 0x80000000,r8
set_cc 0x07 ; Set mask opposite of expected
asr r7,r8
test_cc 1 0 1 0
test_h_gr 0xc0000000,r8
mvi_h_gr 0xdeadbeff,r7 ; Shift by 31
mvi_h_gr 0x80000000,r8
set_cc 0x07 ; Set mask opposite of expected
asr r7,r8
test_cc 1 0 1 0
test_h_gr -1,r8
mvi_h_gr 0xdeadbeff,r7 ; clear register
mvi_h_gr 0x40000000,r8
set_cc 0x0a ; Set mask opposite of expected
asr r7,r8
test_cc 0 1 1 1
test_h_gr 0x00000000,r8
; Test asr $u4Ri
mvi_h_gr 0x80000000,r8
set_cc 0x05 ; Set mask opposite of expected
asr 0,r8
test_cc 1 0 0 0
test_h_gr 0x80000000,r8
mvi_h_gr 0x80000000,r8
set_cc 0x07 ; Set mask opposite of expected
asr 1,r8
test_cc 1 0 1 0
test_h_gr 0xc0000000,r8
mvi_h_gr 0x80000000,r8
set_cc 0x07 ; Set mask opposite of expected
asr 15,r8
test_cc 1 0 1 0
test_h_gr 0xffff0000,r8
mvi_h_gr 0x00004000,r8
set_cc 0x0a ; Set mask opposite of expected
asr 15,r8
test_cc 0 1 1 1
test_h_gr 0x00000000,r8
pass