blob: 72fd04a7009d8fe7bd32782589f1c1838c4230ed [file] [log] [blame]
# frv testcase for rstqf $FRk,@($GRi,$GRj)
# mach: frv
# as(frv): -mcpu=frv
.include "testutils.inc"
start
.global add
add:
; No nesr's active
set_gr_gr sp,gr12
set_mem_limmed 0x2222,0x2222,gr12
set_gr_gr gr12,gr27
inc_gr_immed -4,gr27
set_mem_limmed 0x3333,0x3333,gr27
set_gr_gr gr27,gr26
inc_gr_immed -4,gr26
set_mem_limmed 0x4444,0x4444,gr26
set_gr_gr gr26,gr25
inc_gr_immed -4,gr25
set_mem_limmed 0x5555,0x5555,gr25
set_gr_gr gr25,gr24
inc_gr_immed -4,gr24
set_mem_limmed 0x6666,0x6666,gr24
set_gr_gr gr24,gr23
inc_gr_immed -4,gr23
set_mem_limmed 0x7777,0x7777,gr23
set_gr_gr gr23,gr22
inc_gr_immed -4,gr22
set_mem_limmed 0x8888,0x8888,gr22
set_gr_gr gr22,gr21
inc_gr_immed -4,gr21
set_mem_limmed 0x9999,0x9999,gr21
set_gr_gr gr21,gr20
inc_gr_immed -4,gr20
set_mem_limmed 0xaaaa,0xaaaa,gr20
set_gr_gr gr20,gr19
inc_gr_immed -4,gr19
set_mem_limmed 0xbbbb,0xbbbb,gr19
set_gr_gr gr19,gr18
inc_gr_immed -4,gr18
set_mem_limmed 0xcccc,0xcccc,gr18
set_gr_gr gr18,gr17
inc_gr_immed -4,gr17
set_mem_limmed 0xdddd,0xdddd,gr17
set_gr_gr gr17,gr16
inc_gr_immed -4,gr16
set_mem_limmed 0xeeee,0xeeee,gr16
set_gr_gr gr16,gr15
inc_gr_immed -4,gr15
set_mem_limmed 0xf0f0,0xf0f0,gr15
set_gr_gr gr15,gr14
inc_gr_immed -4,gr14
set_mem_limmed 0xf1f1,0xf1f1,gr14
set_gr_gr gr14,gr13
inc_gr_immed -4,gr13
set_mem_limmed 0xf2f2,0xf2f2,gr13
set_gr_limmed 0x1111,0x1111,gr40
set_gr_limmed 0x1111,0x1111,gr41
set_gr_limmed 0x1111,0x1111,gr42
set_gr_limmed 0x1111,0x1111,gr43
set_fr_iimmed 0x1111,0x1111,fr40
set_fr_iimmed 0x1111,0x1111,fr41
set_fr_iimmed 0x1111,0x1111,fr42
set_fr_iimmed 0x1111,0x1111,fr43
inc_gr_immed -12,sp
set_gr_immed 0,gr7
set_fr_iimmed 0xeeee,0xeeee,fr8
set_fr_iimmed 0xffff,0xffff,fr9
set_fr_iimmed 0xcccc,0xcccc,fr10
set_fr_iimmed 0xdddd,0xdddd,fr11
rstqf fr8,@(sp,gr7)
test_mem_limmed 0xdddd,0xdddd,gr12
test_mem_limmed 0xcccc,0xcccc,gr27
test_mem_limmed 0xffff,0xffff,gr26
test_mem_limmed 0xeeee,0xeeee,gr25
test_mem_limmed 0x6666,0x6666,gr24
test_mem_limmed 0x7777,0x7777,gr23
test_mem_limmed 0x8888,0x8888,gr22
test_mem_limmed 0x9999,0x9999,gr21
test_mem_limmed 0xaaaa,0xaaaa,gr20
test_mem_limmed 0xbbbb,0xbbbb,gr19
test_mem_limmed 0xcccc,0xcccc,gr18
test_mem_limmed 0xdddd,0xdddd,gr17
test_mem_limmed 0xeeee,0xeeee,gr16
test_mem_limmed 0xf0f0,0xf0f0,gr15
test_mem_limmed 0xf1f1,0xf1f1,gr14
test_mem_limmed 0xf2f2,0xf2f2,gr13
test_gr_limmed 0x1111,0x1111,gr40
test_gr_limmed 0x1111,0x1111,gr41
test_gr_limmed 0x1111,0x1111,gr42
test_gr_limmed 0x1111,0x1111,gr43
test_fr_limmed 0x1111,0x1111,fr40
test_fr_limmed 0x1111,0x1111,fr41
test_fr_limmed 0x1111,0x1111,fr42
test_fr_limmed 0x1111,0x1111,fr43
; 1 nesr active with the incorrect address in neear for gr
set_gr_gr sp,gr10
inc_gr_immed -32,gr10
set_gr_immed -32,gr9
nldq @(sp,gr9),gr40
test_spr_gr neear0,gr10
set_mem_limmed 0x2222,0x2222,gr12
set_mem_limmed 0x3333,0x3333,gr27
set_mem_limmed 0x4444,0x4444,gr26
set_mem_limmed 0x5555,0x5555,gr25
set_mem_limmed 0x6666,0x6666,gr24
set_mem_limmed 0x7777,0x7777,gr23
set_mem_limmed 0x8888,0x8888,gr22
set_mem_limmed 0x9999,0x9999,gr21
set_mem_limmed 0xaaaa,0xaaaa,gr20
set_mem_limmed 0xbbbb,0xbbbb,gr19
set_mem_limmed 0xcccc,0xcccc,gr18
set_mem_limmed 0xdddd,0xdddd,gr17
set_mem_limmed 0xeeee,0xeeee,gr16
set_mem_limmed 0xf0f0,0xf0f0,gr15
set_mem_limmed 0xf1f1,0xf1f1,gr14
set_mem_limmed 0xf2f2,0xf2f2,gr13
set_fr_iimmed 0xeeee,0xeeee,fr8
set_fr_iimmed 0xffff,0xffff,fr9
set_fr_iimmed 0xcccc,0xcccc,fr10
set_fr_iimmed 0xdddd,0xdddd,fr11
set_gr_limmed 0x1111,0x1111,gr40
set_gr_limmed 0x1111,0x1111,gr41
set_gr_limmed 0x1111,0x1111,gr42
set_gr_limmed 0x1111,0x1111,gr43
set_fr_iimmed 0x1111,0x1111,fr40
set_fr_iimmed 0x1111,0x1111,fr41
set_fr_iimmed 0x1111,0x1111,fr42
set_fr_iimmed 0x1111,0x1111,fr43
set_gr_immed -16,gr7
rstqf fr8,@(sp,gr7)
test_mem_limmed 0x2222,0x2222,gr12
test_mem_limmed 0x3333,0x3333,gr27
test_mem_limmed 0x4444,0x4444,gr26
test_mem_limmed 0x5555,0x5555,gr25
test_mem_limmed 0xdddd,0xdddd,gr24
test_mem_limmed 0xcccc,0xcccc,gr23
test_mem_limmed 0xffff,0xffff,gr22
test_mem_limmed 0xeeee,0xeeee,gr21
test_mem_limmed 0xaaaa,0xaaaa,gr20
test_mem_limmed 0xbbbb,0xbbbb,gr19
test_mem_limmed 0xcccc,0xcccc,gr18
test_mem_limmed 0xdddd,0xdddd,gr17
test_mem_limmed 0xeeee,0xeeee,gr16
test_mem_limmed 0xf0f0,0xf0f0,gr15
test_mem_limmed 0xf1f1,0xf1f1,gr14
test_mem_limmed 0xf2f2,0xf2f2,gr13
test_gr_limmed 0x1111,0x1111,gr40
test_gr_limmed 0x1111,0x1111,gr41
test_gr_limmed 0x1111,0x1111,gr42
test_gr_limmed 0x1111,0x1111,gr43
test_fr_limmed 0x1111,0x1111,fr40
test_fr_limmed 0x1111,0x1111,fr41
test_fr_limmed 0x1111,0x1111,fr42
test_fr_limmed 0x1111,0x1111,fr43
; 1 nesr active with the incorrect address in neear for fr
inc_gr_immed -16,gr10
nlddfi @(sp,-48),fr40
test_spr_gr neear1,gr10
set_mem_limmed 0x2222,0x2222,gr12
set_mem_limmed 0x3333,0x3333,gr27
set_mem_limmed 0x4444,0x4444,gr26
set_mem_limmed 0x5555,0x5555,gr25
set_mem_limmed 0x6666,0x6666,gr24
set_mem_limmed 0x7777,0x7777,gr23
set_mem_limmed 0x8888,0x8888,gr22
set_mem_limmed 0x9999,0x9999,gr21
set_mem_limmed 0xaaaa,0xaaaa,gr20
set_mem_limmed 0xbbbb,0xbbbb,gr19
set_mem_limmed 0xcccc,0xcccc,gr18
set_mem_limmed 0xdddd,0xdddd,gr17
set_mem_limmed 0xeeee,0xeeee,gr16
set_mem_limmed 0xf0f0,0xf0f0,gr15
set_mem_limmed 0xf1f1,0xf1f1,gr14
set_mem_limmed 0xf2f2,0xf2f2,gr13
set_fr_iimmed 0xeeee,0xeeee,fr8
set_fr_iimmed 0xffff,0xffff,fr9
set_fr_iimmed 0xcccc,0xcccc,fr10
set_fr_iimmed 0xdddd,0xdddd,fr11
set_gr_limmed 0x1111,0x1111,gr40
set_gr_limmed 0x1111,0x1111,gr41
set_gr_limmed 0x1111,0x1111,gr42
set_gr_limmed 0x1111,0x1111,gr43
set_fr_iimmed 0x1111,0x1111,fr40
set_fr_iimmed 0x1111,0x1111,fr41
set_fr_iimmed 0x1111,0x1111,fr42
set_fr_iimmed 0x1111,0x1111,fr43
inc_gr_immed -16,sp
set_gr_immed 16,gr7
rstqf fr8,@(sp,gr7)
test_mem_limmed 0xdddd,0xdddd,gr12
test_mem_limmed 0xcccc,0xcccc,gr27
test_mem_limmed 0xffff,0xffff,gr26
test_mem_limmed 0xeeee,0xeeee,gr25
test_mem_limmed 0x6666,0x6666,gr24
test_mem_limmed 0x7777,0x7777,gr23
test_mem_limmed 0x8888,0x8888,gr22
test_mem_limmed 0x9999,0x9999,gr21
test_mem_limmed 0xaaaa,0xaaaa,gr20
test_mem_limmed 0xbbbb,0xbbbb,gr19
test_mem_limmed 0xcccc,0xcccc,gr18
test_mem_limmed 0xdddd,0xdddd,gr17
test_mem_limmed 0xeeee,0xeeee,gr16
test_mem_limmed 0xf0f0,0xf0f0,gr15
test_mem_limmed 0xf1f1,0xf1f1,gr14
test_mem_limmed 0xf2f2,0xf2f2,gr13
test_gr_limmed 0x1111,0x1111,gr40
test_gr_limmed 0x1111,0x1111,gr41
test_gr_limmed 0x1111,0x1111,gr42
test_gr_limmed 0x1111,0x1111,gr43
test_fr_limmed 0x1111,0x1111,fr40
test_fr_limmed 0x1111,0x1111,fr41
test_fr_limmed 0x1111,0x1111,fr42
test_fr_limmed 0x1111,0x1111,fr43
; 1 nesr active with the correct address in neear for gr
set_mem_limmed 0x2222,0x2222,gr12
set_mem_limmed 0x3333,0x3333,gr27
set_mem_limmed 0x4444,0x4444,gr26
set_mem_limmed 0x5555,0x5555,gr25
set_mem_limmed 0x6666,0x6666,gr24
set_mem_limmed 0x7777,0x7777,gr23
set_mem_limmed 0x8888,0x8888,gr22
set_mem_limmed 0x9999,0x9999,gr21
set_mem_limmed 0xaaaa,0xaaaa,gr20
set_mem_limmed 0xbbbb,0xbbbb,gr19
set_mem_limmed 0xcccc,0xcccc,gr18
set_mem_limmed 0xdddd,0xdddd,gr17
set_mem_limmed 0xeeee,0xeeee,gr16
set_mem_limmed 0xf0f0,0xf0f0,gr15
set_mem_limmed 0xf1f1,0xf1f1,gr14
set_mem_limmed 0xf2f2,0xf2f2,gr13
set_fr_iimmed 0xeeee,0xeeee,fr8
set_fr_iimmed 0xffff,0xffff,fr9
set_fr_iimmed 0xcccc,0xcccc,fr10
set_fr_iimmed 0xdddd,0xdddd,fr11
set_gr_limmed 0x1111,0x1111,gr40
set_gr_limmed 0x1111,0x1111,gr41
set_gr_limmed 0x1111,0x1111,gr42
set_gr_limmed 0x1111,0x1111,gr43
set_fr_iimmed 0x1111,0x1111,fr40
set_fr_iimmed 0x1111,0x1111,fr41
set_fr_iimmed 0x1111,0x1111,fr42
set_fr_iimmed 0x1111,0x1111,fr43
inc_gr_immed -16,sp
set_gr_immed 0,gr7
rstqf fr8,@(sp,gr7)
test_mem_limmed 0x2222,0x2222,gr12
test_mem_limmed 0x3333,0x3333,gr27
test_mem_limmed 0x4444,0x4444,gr26
test_mem_limmed 0x5555,0x5555,gr25
test_mem_limmed 0x6666,0x6666,gr24
test_mem_limmed 0x7777,0x7777,gr23
test_mem_limmed 0x8888,0x8888,gr22
test_mem_limmed 0x9999,0x9999,gr21
test_mem_limmed 0xdddd,0xdddd,gr20
test_mem_limmed 0xcccc,0xcccc,gr19
test_mem_limmed 0xffff,0xffff,gr18
test_mem_limmed 0xeeee,0xeeee,gr17
test_mem_limmed 0xeeee,0xeeee,gr16
test_mem_limmed 0xf0f0,0xf0f0,gr15
test_mem_limmed 0xf1f1,0xf1f1,gr14
test_mem_limmed 0xf2f2,0xf2f2,gr13
test_gr_limmed 0xeeee,0xeeee,gr40
test_gr_limmed 0xffff,0xffff,gr41
test_gr_limmed 0xcccc,0xcccc,gr42
test_gr_limmed 0xdddd,0xdddd,gr43
test_fr_limmed 0x1111,0x1111,fr40
test_fr_limmed 0x1111,0x1111,fr41
test_fr_limmed 0x1111,0x1111,fr42
test_fr_limmed 0x1111,0x1111,fr43
; 1 nesr active with the correct address in neear for fr
set_mem_limmed 0x2222,0x2222,gr12
set_mem_limmed 0x3333,0x3333,gr27
set_mem_limmed 0x4444,0x4444,gr26
set_mem_limmed 0x5555,0x5555,gr25
set_mem_limmed 0x6666,0x6666,gr24
set_mem_limmed 0x7777,0x7777,gr23
set_mem_limmed 0x8888,0x8888,gr22
set_mem_limmed 0x9999,0x9999,gr21
set_mem_limmed 0xaaaa,0xaaaa,gr20
set_mem_limmed 0xbbbb,0xbbbb,gr19
set_mem_limmed 0xcccc,0xcccc,gr18
set_mem_limmed 0xdddd,0xdddd,gr17
set_mem_limmed 0xeeee,0xeeee,gr16
set_mem_limmed 0xf0f0,0xf0f0,gr15
set_mem_limmed 0xf1f1,0xf1f1,gr14
set_mem_limmed 0xf2f2,0xf2f2,gr13
set_fr_iimmed 0xeeee,0xeeee,fr8
set_fr_iimmed 0xffff,0xffff,fr9
set_fr_iimmed 0xcccc,0xcccc,fr10
set_fr_iimmed 0xdddd,0xdddd,fr11
set_gr_limmed 0x1111,0x1111,gr40
set_gr_limmed 0x1111,0x1111,gr41
set_gr_limmed 0x1111,0x1111,gr42
set_gr_limmed 0x1111,0x1111,gr43
set_fr_iimmed 0x1111,0x1111,fr40
set_fr_iimmed 0x1111,0x1111,fr41
set_fr_iimmed 0x1111,0x1111,fr42
set_fr_iimmed 0x1111,0x1111,fr43
set_gr_immed -16,gr7
rstqf fr8,@(sp,gr7)
test_mem_limmed 0x2222,0x2222,gr12
test_mem_limmed 0x3333,0x3333,gr27
test_mem_limmed 0x4444,0x4444,gr26
test_mem_limmed 0x5555,0x5555,gr25
test_mem_limmed 0x6666,0x6666,gr24
test_mem_limmed 0x7777,0x7777,gr23
test_mem_limmed 0x8888,0x8888,gr22
test_mem_limmed 0x9999,0x9999,gr21
test_mem_limmed 0xaaaa,0xaaaa,gr20
test_mem_limmed 0xbbbb,0xbbbb,gr19
test_mem_limmed 0xcccc,0xcccc,gr18
test_mem_limmed 0xdddd,0xdddd,gr17
test_mem_limmed 0xdddd,0xdddd,gr16
test_mem_limmed 0xcccc,0xcccc,gr15
test_mem_limmed 0xffff,0xffff,gr14
test_mem_limmed 0xeeee,0xeeee,gr13
test_gr_limmed 0x1111,0x1111,gr40
test_gr_limmed 0x1111,0x1111,gr41
test_gr_limmed 0x1111,0x1111,gr42
test_gr_limmed 0x1111,0x1111,gr43
test_fr_limmed 0xeeee,0xeeee,fr40
test_fr_limmed 0xffff,0xffff,fr41
test_fr_limmed 0xcccc,0xcccc,fr42
test_fr_limmed 0xdddd,0xdddd,fr43
pass