| # Intel(r) Wireless MMX(tm) technology testcase for WADD |
| # mach: xscale |
| # as: -mcpu=xscale+iwmmxt |
| |
| .include "testutils.inc" |
| |
| start |
| |
| .global wadd |
| wadd: |
| # Enable access to CoProcessors 0 & 1 before |
| # we attempt these instructions. |
| |
| mvi_h_gr r1, 3 |
| mcr p15, 0, r1, cr15, cr1, 0 |
| |
| # Test UnSaturated Byte Addition |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| waddb wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x23456789 |
| test_h_gr r5, 0xabcdef11 |
| |
| # Test Unsigned Saturated Byte Addition |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| waddbus wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x23456789 |
| test_h_gr r5, 0xabcdef11 |
| |
| # Test Signed Saturated Byte Addition |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| waddbss wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x2345677f |
| test_h_gr r5, 0xabcdef11 |
| |
| # Test UnSaturated Halfword Addition |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| waddh wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x23456789 |
| test_h_gr r5, 0xabcdef11 |
| |
| # Test Unsigned Saturated Halfword Addition |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| waddhus wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x23456789 |
| test_h_gr r5, 0xabcdef11 |
| |
| # Test Signed Saturated Halfword Addition |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| waddhss wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x23456789 |
| test_h_gr r5, 0xabcdef11 |
| |
| # Test UnSaturated Word Addition |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| waddw wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x23456789 |
| test_h_gr r5, 0xabcdef11 |
| |
| # Test Unsigned Saturated Word Addition |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| waddwus wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x23456789 |
| test_h_gr r5, 0xabcdef11 |
| |
| # Test Signed Saturated Word Addition |
| |
| mvi_h_gr r0, 0x12345678 |
| mvi_h_gr r1, 0x9abcde00 |
| mvi_h_gr r2, 0x11111111 |
| mvi_h_gr r3, 0x11111111 |
| mvi_h_gr r4, 0 |
| mvi_h_gr r5, 0 |
| |
| tmcrr wr0, r0, r1 |
| tmcrr wr1, r2, r3 |
| tmcrr wr2, r4, r5 |
| |
| waddwss wr2, wr0, wr1 |
| |
| tmrrc r0, r1, wr0 |
| tmrrc r2, r3, wr1 |
| tmrrc r4, r5, wr2 |
| |
| test_h_gr r0, 0x12345678 |
| test_h_gr r1, 0x9abcde00 |
| test_h_gr r2, 0x11111111 |
| test_h_gr r3, 0x11111111 |
| test_h_gr r4, 0x23456789 |
| test_h_gr r5, 0xabcdef11 |
| |
| pass |
