# frv testcase for mqxmachs $GRi,$GRj,$ACCk
# mach: fr400

	.include "testutils.inc"

	start

	.global mqxmachs
mqxmachs:
	; Positive operands
	set_fr_iimmed  	2,3,fr8		; multiply small numbers
	set_fr_iimmed  	3,2,fr10
	set_fr_iimmed  	0,1,fr9		; multiply by 0
	set_fr_iimmed  	2,0,fr11
	mqxmachs      	fr8,fr10,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg0
	test_acc_immed 	0,acc0
	test_accg_immed 	0,accg1
	test_acc_immed 	0,acc1
	test_accg_immed 	0,accg2
	test_acc_immed 	6,acc2
	test_accg_immed 	0,accg3
	test_acc_immed 	6,acc3

	set_fr_iimmed  	2,1,fr8		; multiply by 1
	set_fr_iimmed  	1,2,fr10
	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
	set_fr_iimmed  	2,0x3fff,fr11
	mqxmachs      	fr8,fr10,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg2
	test_acc_immed 	8,acc2
	test_accg_immed 	0,accg3
	test_acc_immed 	8,acc3
	test_accg_immed 	0,accg0
	test_acc_limmed	0,0x7ffe,acc0
	test_accg_immed 	0,accg1
	test_acc_limmed	0,0x7ffe,acc1

	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
	set_fr_iimmed  	2,0x4000,fr10
	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
	set_fr_iimmed	0x7fff,0x7fff,fr11
	mqxmachs      	fr8,fr10,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg2
	test_acc_limmed	0x0000,0x8008,acc2
	test_accg_immed 	0,accg3
	test_acc_limmed	0x0000,0x8008,acc3
	test_accg_immed 	0,accg0
	test_acc_limmed 0x3fff,0x7fff,acc0
	test_accg_immed 	0,accg1
	test_acc_limmed 0x3fff,0x7fff,acc1

	; Mixed operands
	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
	set_fr_iimmed  	0xfffd,2,fr10
	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
	set_fr_iimmed  	1,0xfffe,fr11
	mqxmachs      	fr8,fr10,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg2
	test_acc_limmed 0x0000,0x8002,acc2
	test_accg_immed 	0,accg3
	test_acc_limmed 0x0000,0x8002,acc3
	test_accg_immed 	0,accg0
	test_acc_limmed 0x3fff,0x7ffd,acc0
	test_accg_immed 	0,accg1
	test_acc_limmed 0x3fff,0x7ffd,acc1

	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
	set_fr_iimmed  	0,0xfffe,fr10
	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
	set_fr_iimmed  	0xfffe,0x2001,fr11
	mqxmachs      	fr8,fr10,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg2
	test_acc_limmed 0x0000,0x8002,acc2
	test_accg_immed 	0,accg3
	test_acc_limmed 0x0000,0x8002,acc3
	test_accg_immed 	0,accg0
	test_acc_limmed	0x3fff,0x3ffb,acc0
	test_accg_immed 	0,accg1
	test_acc_limmed	0x3fff,0x3ffb,acc1

	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
	set_fr_iimmed  	0xfffe,0x4000,fr10
	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
	set_fr_iimmed	0x8000,0x7fff,fr11
	mqxmachs      	fr8,fr10,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg2
	test_acc_limmed	0x0000,0x0002,acc2
	test_accg_immed 	0,accg3
	test_acc_limmed	0x0000,0x0002,acc3
	test_accg_immed 	0xff,accg0
	test_acc_limmed	0xffff,0xbffb,acc0
	test_accg_immed 	0xff,accg1
	test_acc_limmed	0xffff,0xbffb,acc1

	; Negative operands
	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
	set_fr_iimmed  	0xfffd,0xfffe,fr10
	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
	set_fr_iimmed  	0xfffe,0xffff,fr11
	mqxmachs      	fr8,fr10,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg2
	test_acc_limmed	0x0000,0x0008,acc2
	test_accg_immed 	0,accg3
	test_acc_limmed	0x0000,0x0008,acc3
	test_accg_immed 	0xff,accg0
	test_acc_limmed	0xffff,0xbffd,acc0
	test_accg_immed 	0xff,accg1
	test_acc_limmed	0xffff,0xbffd,acc1

	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
	set_fr_iimmed	0x8001,0x8001,fr10
	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
	set_fr_iimmed	0x8000,0x8000,fr11
	mqxmachs      	fr8,fr10,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg2
	test_acc_immed 	0x3fff0009,acc2
	test_accg_immed 	0,accg3
	test_acc_immed 	0x3fff0009,acc3
	test_accg_immed 	0,accg0
	test_acc_immed 	0x3fffbffd,acc0
	test_accg_immed 	0,accg1
	test_acc_immed 	0x3fffbffd,acc1

	set_accg_immed 	0x7f,accg2		; saturation
	set_acc_immed	0xffffffff,acc2
	set_accg_immed 	0x7f,accg3
	set_acc_immed	0xffffffff,acc3
	set_accg_immed 	0x7f,accg0		; saturation
	set_acc_immed	0xffffffff,acc0
	set_accg_immed 	0x7f,accg1
	set_acc_immed	0xffffffff,acc1
	set_fr_iimmed  	1,1,fr8
	set_fr_iimmed  	1,1,fr10
	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
	set_fr_iimmed  	0x7fff,0x7fff,fr11
	mqxmachs      	fr8,fr10,acc0
	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
	test_accg_immed 	0x7f,accg2
	test_acc_limmed	0xffff,0xffff,acc2
	test_accg_immed 	0x7f,accg3
	test_acc_limmed	0xffff,0xffff,acc3
	test_accg_immed 	0x7f,accg0
	test_acc_limmed	0xffff,0xffff,acc0
	test_accg_immed 	0x7f,accg1
	test_acc_limmed	0xffff,0xffff,acc1

	set_accg_immed 	0x80,accg2		; saturation
	set_acc_immed	0,acc2
	set_accg_immed 	0x80,accg3
	set_acc_immed	0,acc3
	set_accg_immed 	0x80,accg0		; saturation
	set_acc_immed	0,acc0
	set_accg_immed 	0x80,accg1
	set_acc_immed	0,acc1
	set_fr_iimmed  	0xffff,0,fr8
	set_fr_iimmed  	1,0xffff,fr10
	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
	set_fr_iimmed  	0x7fff,0x7fff,fr11
	mqxmachs      	fr8,fr10,acc0
	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
	test_accg_immed 	0x80,accg2
	test_acc_immed	0,acc2
	test_accg_immed 	0x80,accg3
	test_acc_immed	0,acc3
	test_accg_immed 	0x80,accg0
	test_acc_immed	0,acc0
	test_accg_immed 	0x80,accg1
	test_acc_immed	0,acc1

	pass