)]}'
{
  "commit": "0748d2c83fc0440f101fe01cc3dfc97c8e11c3b2",
  "tree": "bb702c0a9d8f48d5c44885a8c36d277ff5c4f565",
  "parents": [
    "8a1346f379a15dc8b79e50656dc5d8728336231c"
  ],
  "author": {
    "name": "Luke Zhuang",
    "email": "luke.zhuang@linux.alibaba.com",
    "time": "Thu Jun 25 13:45:16 2026 +0800"
  },
  "committer": {
    "name": "Kito Cheng",
    "email": "kito.cheng@sifive.com",
    "time": "Wed Jul 15 17:29:14 2026 +0800"
  },
  "message": "RISC-V: Declare TLSDESC clobbers for vector registers and CSRs per psABI\n\nPer the RISC-V psABI, the TLSDESC resolver clobbers a0 and t0 in the\nbase case.  With the new psABI update\n(https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/496),\nwhen the V extension is enabled, it additionally clobbers all vector\nregisters and vector CSRs.\n\nThis patch updates the clobbering of tlsdesc define_insn: clobbering\nnot only a0 and t0, but also all V-regs (using 4 x LMUL8 reg\ngroups covering all 32 physical V-regs), and 4 vector CSRs\n(vl/vtype/vxrm/vxstat).\n\nThree new tests are added covering GPR, vector register, and vector\nCSR clobber behavior.\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv.md (VXSAT_REGNUM): New constant.\n\t(@tlsdesc\u003cmode\u003e): update clobbering.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/tlsdesc_clobber.c: New test.\n\t* gcc.target/riscv/tlsdesc_clobber_v.c: New test.\n\t* gcc.target/riscv/tlsdesc_clobber_v_csr.c: New test.\n",
  "tree_diff": [
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