)]}'
{
  "commit": "24b2b8ee6bb628def56a67c18c4675e78f2d2cb6",
  "tree": "beaeb4a7e3f7cc4264b0db9c71cd843cc1e8e651",
  "parents": [
    "c3b9dc79868a7b3a92753a61cfb7625a1d2aa291"
  ],
  "author": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Thu Aug 27 08:37:17 2026 +0800"
  },
  "committer": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Fri Aug 28 08:45:35 2026 +0800"
  },
  "message": "RISC-V: Add test cases for vwmaccu.vx reg overlap\n\nAdd test cases for register group overlap, please\nnote it is not overlap as much as possible.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-mf2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf8.c: New test.\n\nSigned-off-by: Pan Li \u003cpan2.li@intel.com\u003e\n",
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