)]}'
{
  "commit": "37f0e8395c279b5eb969bf678e5c571c1f3d3b32",
  "tree": "0ed94734d5d70cf8dfbabbbfdad4346069ee5763",
  "parents": [
    "6a2a0ab8b71e0985f6950f450f8c34437a2fbdcc"
  ],
  "author": {
    "name": "Jiawei",
    "email": "jiawei@iscas.ac.cn",
    "time": "Thu Jun 05 13:46:39 2025 +0800"
  },
  "committer": {
    "name": "Jiawei",
    "email": "jiawei@iscas.ac.cn",
    "time": "Thu Jun 05 19:33:25 2025 +0800"
  },
  "message": "RISC-V: Support Sstvala extension.\n\nSupport the Sstvala extension, which provides all needed values in\nSupervisor Trap Value register (stval).\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-ext.def: New extension definition.\n\t* config/riscv/riscv-ext.opt: New extension mask.\n\t* doc/riscv-ext.texi: Document the new extension.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/arch-sstvala.c: New test.\n\nSigned-off-by: Jiawei \u003cjiawei@iscas.ac.cn\u003e\n",
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