gcc/config/aarch64/aarch64-sve.md

;; Machine description for AArch64 SVE. ;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. ;; ;; GCC is free software; you can redistribute it and/or modify it ;; under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 3, or (at your option) ;; any later version. ;; ;; GCC is distributed in the hope that it will be useful, but ;; WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ;; General Public License for more details. ;; ;; You should have received a copy of the GNU General Public License ;; along with GCC; see the file COPYING3. If not see ;; http://www.gnu.org/licenses/.

;; Note on the handling of big-endian SVE ;; -------------------------------------- ;; ;; On big-endian systems, Advanced SIMD mov patterns act in the ;; same way as movdi or movti would: the first byte of memory goes ;; into the most significant byte of the register and the last byte ;; of memory goes into the least significant byte of the register. ;; This is the most natural ordering for Advanced SIMD and matches ;; the ABI layout for 64-bit and 128-bit vector types. ;; ;; As a result, the order of bytes within the register is what GCC ;; expects for a big-endian target, and subreg offsets therefore work ;; as expected, with the first element in memory having subreg offset 0 ;; and the last element in memory having the subreg offset associated ;; with a big-endian lowpart. However, this ordering also means that ;; GCC‘s lane numbering does not match the architecture’s numbering: ;; GCC always treats the element at the lowest address in memory ;; (subreg offset 0) as element 0, while the architecture treats ;; the least significant end of the register as element 0. ;; ;; The situation for SVE is different. We want the layout of the ;; SVE register to be same for mov as it is for maskload: ;; logically, a mov load must be indistinguishable from a ;; maskload whose mask is all true. We therefore need the ;; register layout to match LD1 rather than LDR. The ABI layout of ;; SVE types also matches LD1 byte ordering rather than LDR byte ordering. ;; ;; As a result, the architecture lane numbering matches GCC's lane ;; numbering, with element 0 always being the first in memory. ;; However: ;; ;; - Applying a subreg offset to a register does not give the element ;; that GCC expects: the first element in memory has the subreg offset ;; associated with a big-endian lowpart while the last element in memory ;; has subreg offset 0. We handle this via TARGET_CAN_CHANGE_MODE_CLASS. ;; ;; - We cannot use LDR and STR for spill slots that might be accessed ;; via subregs, since although the elements have the order GCC expects, ;; the order of the bytes within the elements is different. We instead ;; access spill slots via LD1 and ST1, using secondary reloads to ;; reserve a predicate register.

;; SVE data moves. (define_expand “mov” [(set (match_operand:SVE_ALL 0 “nonimmediate_operand”) (match_operand:SVE_ALL 1 “general_operand”))] “TARGET_SVE” { /* Use the predicated load and store patterns where possible. This is required for big-endian targets (see the comment at the head of the file) and increases the addressing choices for little-endian. */ if ((MEM_P (operands[0]) || MEM_P (operands[1])) && can_create_pseudo_p ()) { aarch64_expand_sve_mem_move (operands[0], operands[1], mode); DONE; }

if (CONSTANT_P (operands[1]))
  {
aarch64_expand_mov_immediate (operands[0], operands[1],
			      gen_vec_duplicate<mode>);
DONE;
  }

/* Optimize subregs on big-endian targets: we can use REV[BHW]
   instead of going through memory.  */
if (BYTES_BIG_ENDIAN
    && aarch64_maybe_expand_sve_subreg_move (operands[0], operands[1]))
  DONE;

} )

;; A pattern for optimizing SUBREGs that have a reinterpreting effect ;; on big-endian targets; see aarch64_maybe_expand_sve_subreg_move ;; for details. We use a special predicate for operand 2 to reduce ;; the number of patterns. (define_insn_and_split “*aarch64_sve_mov_subreg_be” [(set (match_operand:SVE_ALL 0 “aarch64_sve_nonimmediate_operand” “=w”) (unspec:SVE_ALL [(match_operand:VNx16BI 1 “register_operand” “Upl”) (match_operand 2 “aarch64_any_register_operand” “w”)] UNSPEC_REV_SUBREG))] “TARGET_SVE && BYTES_BIG_ENDIAN” “#” “&& reload_completed” [(const_int 0)] { aarch64_split_sve_subreg_move (operands[0], operands[1], operands[2]); DONE; } )

;; Unpredicated moves (little-endian). Only allow memory operations ;; during and after RA; before RA we want the predicated load and ;; store patterns to be used instead. (define_insn “*aarch64_sve_mov_le” [(set (match_operand:SVE_ALL 0 “aarch64_sve_nonimmediate_operand” “=w, Utr, w, w”) (match_operand:SVE_ALL 1 “aarch64_sve_general_operand” “Utr, w, w, Dn”))] “TARGET_SVE && !BYTES_BIG_ENDIAN && ((lra_in_progress || reload_completed) || (register_operand (operands[0], mode) && nonmemory_operand (operands[1], mode)))” "@ ldr\t%0, %1 str\t%1, %0 mov\t%0.d, %1.d

return aarch64_output_sve_mov_immediate (operands[1]);" )

;; Unpredicated moves (big-endian). Memory accesses require secondary ;; reloads. (define_insn “*aarch64_sve_mov_be” [(set (match_operand:SVE_ALL 0 “register_operand” “=w, w”) (match_operand:SVE_ALL 1 “aarch64_nonmemory_operand” “w, Dn”))] “TARGET_SVE && BYTES_BIG_ENDIAN” "@ mov\t%0.d, %1.d

return aarch64_output_sve_mov_immediate (operands[1]);" )

;; Handle big-endian memory reloads. We use byte PTRUE for all modes ;; to try to encourage reuse. (define_expand “aarch64_sve_reload_be” [(parallel [(set (match_operand 0) (match_operand 1)) (clobber (match_operand:VNx16BI 2 “register_operand” “=Upl”))])] “TARGET_SVE && BYTES_BIG_ENDIAN” { /* Create a PTRUE. */ emit_move_insn (operands[2], CONSTM1_RTX (VNx16BImode));

/* Refer to the PTRUE in the appropriate mode for this move.  */
machine_mode mode = GET_MODE (operands[0]);
machine_mode pred_mode
  = aarch64_sve_pred_mode (GET_MODE_UNIT_SIZE (mode)).require ();
rtx pred = gen_lowpart (pred_mode, operands[2]);

/* Emit a predicated load or store.  */
aarch64_emit_sve_pred_move (operands[0], pred, operands[1]);
DONE;

} )

;; A predicated load or store for which the predicate is known to be ;; all-true. Note that this pattern is generated directly by ;; aarch64_emit_sve_pred_move, so changes to this pattern will ;; need changes there as well. (define_insn “*pred_mov” [(set (match_operand:SVE_ALL 0 “nonimmediate_operand” “=w, m”) (unspec:SVE_ALL [(match_operand: 1 “register_operand” “Upl, Upl”) (match_operand:SVE_ALL 2 “nonimmediate_operand” “m, w”)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE && (register_operand (operands[0], mode) || register_operand (operands[2], mode))” “@ ld1\t%0., %1/z, %2 st1\t%2., %1, %0” )

(define_expand “movmisalign” [(set (match_operand:SVE_ALL 0 “nonimmediate_operand”) (match_operand:SVE_ALL 1 “general_operand”))] “TARGET_SVE” { /* Equivalent to a normal move for our purpooses. */ emit_move_insn (operands[0], operands[1]); DONE; } )

(define_insn “maskload” [(set (match_operand:SVE_ALL 0 “register_operand” “=w”) (unspec:SVE_ALL [(match_operand: 2 “register_operand” “Upl”) (match_operand:SVE_ALL 1 “memory_operand” “m”)] UNSPEC_LD1_SVE))] “TARGET_SVE” “ld1\t%0., %2/z, %1” )

(define_insn “maskstore” [(set (match_operand:SVE_ALL 0 “memory_operand” “+m”) (unspec:SVE_ALL [(match_operand: 2 “register_operand” “Upl”) (match_operand:SVE_ALL 1 “register_operand” “w”) (match_dup 0)] UNSPEC_ST1_SVE))] “TARGET_SVE” “st1\t%1., %2, %0” )

;; Unpredicated gather loads. (define_expand “gather_load” [(set (match_operand:SVE_SD 0 “register_operand”) (unspec:SVE_SD [(match_dup 5) (match_operand:DI 1 “aarch64_reg_or_zero”) (match_operand:<V_INT_EQUIV> 2 “register_operand”) (match_operand:DI 3 “const_int_operand”) (match_operand:DI 4 “aarch64_gather_scale_operand_”) (mem:BLK (scratch))] UNSPEC_LD1_GATHER))] “TARGET_SVE” { operands[5] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated gather loads for 32-bit elements. Operand 3 is true for ;; unsigned extension and false for signed extension. (define_insn “mask_gather_load” [(set (match_operand:SVE_S 0 “register_operand” “=w, w, w, w, w”) (unspec:SVE_S [(match_operand: 5 “register_operand” “Upl, Upl, Upl, Upl, Upl”) (match_operand:DI 1 “aarch64_reg_or_zero” “Z, rk, rk, rk, rk”) (match_operand:<V_INT_EQUIV> 2 “register_operand” “w, w, w, w, w”) (match_operand:DI 3 “const_int_operand” “i, Z, Ui1, Z, Ui1”) (match_operand:DI 4 “aarch64_gather_scale_operand_w” “Ui1, Ui1, Ui1, i, i”) (mem:BLK (scratch))] UNSPEC_LD1_GATHER))] “TARGET_SVE” “@ ld1w\t%0.s, %5/z, [%2.s] ld1w\t%0.s, %5/z, [%1, %2.s, sxtw] ld1w\t%0.s, %5/z, [%1, %2.s, uxtw] ld1w\t%0.s, %5/z, [%1, %2.s, sxtw %p4] ld1w\t%0.s, %5/z, [%1, %2.s, uxtw %p4]” )

;; Predicated gather loads for 64-bit elements. The value of operand 3 ;; doesn't matter in this case. (define_insn “mask_gather_load” [(set (match_operand:SVE_D 0 “register_operand” “=w, w, w”) (unspec:SVE_D [(match_operand: 5 “register_operand” “Upl, Upl, Upl”) (match_operand:DI 1 “aarch64_reg_or_zero” “Z, rk, rk”) (match_operand:<V_INT_EQUIV> 2 “register_operand” “w, w, w”) (match_operand:DI 3 “const_int_operand”) (match_operand:DI 4 “aarch64_gather_scale_operand_d” “Ui1, Ui1, i”) (mem:BLK (scratch))] UNSPEC_LD1_GATHER))] “TARGET_SVE” “@ ld1d\t%0.d, %5/z, [%2.d] ld1d\t%0.d, %5/z, [%1, %2.d] ld1d\t%0.d, %5/z, [%1, %2.d, lsl %p4]” )

;; Unpredicated scatter store. (define_expand “scatter_store” [(set (mem:BLK (scratch)) (unspec:BLK [(match_dup 5) (match_operand:DI 0 “aarch64_reg_or_zero”) (match_operand:<V_INT_EQUIV> 1 “register_operand”) (match_operand:DI 2 “const_int_operand”) (match_operand:DI 3 “aarch64_gather_scale_operand_”) (match_operand:SVE_SD 4 “register_operand”)] UNSPEC_ST1_SCATTER))] “TARGET_SVE” { operands[5] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated scatter stores for 32-bit elements. Operand 2 is true for ;; unsigned extension and false for signed extension. (define_insn “mask_scatter_store” [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand: 5 “register_operand” “Upl, Upl, Upl, Upl, Upl”) (match_operand:DI 0 “aarch64_reg_or_zero” “Z, rk, rk, rk, rk”) (match_operand:<V_INT_EQUIV> 1 “register_operand” “w, w, w, w, w”) (match_operand:DI 2 “const_int_operand” “i, Z, Ui1, Z, Ui1”) (match_operand:DI 3 “aarch64_gather_scale_operand_w” “Ui1, Ui1, Ui1, i, i”) (match_operand:SVE_S 4 “register_operand” “w, w, w, w, w”)] UNSPEC_ST1_SCATTER))] “TARGET_SVE” “@ st1w\t%4.s, %5, [%1.s] st1w\t%4.s, %5, [%0, %1.s, sxtw] st1w\t%4.s, %5, [%0, %1.s, uxtw] st1w\t%4.s, %5, [%0, %1.s, sxtw %p3] st1w\t%4.s, %5, [%0, %1.s, uxtw %p3]” )

;; Predicated scatter stores for 64-bit elements. The value of operand 2 ;; doesn't matter in this case. (define_insn “mask_scatter_store” [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand: 5 “register_operand” “Upl, Upl, Upl”) (match_operand:DI 0 “aarch64_reg_or_zero” “Z, rk, rk”) (match_operand:<V_INT_EQUIV> 1 “register_operand” “w, w, w”) (match_operand:DI 2 “const_int_operand”) (match_operand:DI 3 “aarch64_gather_scale_operand_d” “Ui1, Ui1, i”) (match_operand:SVE_D 4 “register_operand” “w, w, w”)] UNSPEC_ST1_SCATTER))] “TARGET_SVE” “@ st1d\t%4.d, %5, [%1.d] st1d\t%4.d, %5, [%0, %1.d] st1d\t%4.d, %5, [%0, %1.d, lsl %p3]” )

;; SVE structure moves. (define_expand “mov” [(set (match_operand:SVE_STRUCT 0 “nonimmediate_operand”) (match_operand:SVE_STRUCT 1 “general_operand”))] “TARGET_SVE” { /* Big-endian loads and stores need to be done via LD1 and ST1; see the comment at the head of the file for details. */ if ((MEM_P (operands[0]) || MEM_P (operands[1])) && BYTES_BIG_ENDIAN) { gcc_assert (can_create_pseudo_p ()); aarch64_expand_sve_mem_move (operands[0], operands[1], mode); DONE; }

if (CONSTANT_P (operands[1]))
  {
aarch64_expand_mov_immediate (operands[0], operands[1]);
DONE;
  }

} )

;; Unpredicated structure moves (little-endian). (define_insn “*aarch64_sve_mov_le” [(set (match_operand:SVE_STRUCT 0 “aarch64_sve_nonimmediate_operand” “=w, Utr, w, w”) (match_operand:SVE_STRUCT 1 “aarch64_sve_general_operand” “Utr, w, w, Dn”))] “TARGET_SVE && !BYTES_BIG_ENDIAN” “#” [(set_attr “length” “<insn_length>”)] )

;; Unpredicated structure moves (big-endian). Memory accesses require ;; secondary reloads. (define_insn “*aarch64_sve_mov_le” [(set (match_operand:SVE_STRUCT 0 “register_operand” “=w, w”) (match_operand:SVE_STRUCT 1 “aarch64_nonmemory_operand” “w, Dn”))] “TARGET_SVE && BYTES_BIG_ENDIAN” “#” [(set_attr “length” “<insn_length>”)] )

;; Split unpredicated structure moves into pieces. This is the same ;; for both big-endian and little-endian code, although it only needs ;; to handle memory operands for little-endian code. (define_split [(set (match_operand:SVE_STRUCT 0 “aarch64_sve_nonimmediate_operand”) (match_operand:SVE_STRUCT 1 “aarch64_sve_general_operand”))] “TARGET_SVE && reload_completed” [(const_int 0)] { rtx dest = operands[0]; rtx src = operands[1]; if (REG_P (dest) && REG_P (src)) aarch64_simd_emit_reg_reg_move (operands, mode, <vector_count>); else for (unsigned int i = 0; i < <vector_count>; ++i) { rtx subdest = simplify_gen_subreg (mode, dest, mode, i * BYTES_PER_SVE_VECTOR); rtx subsrc = simplify_gen_subreg (mode, src, mode, i * BYTES_PER_SVE_VECTOR); emit_insn (gen_rtx_SET (subdest, subsrc)); } DONE; } )

;; Predicated structure moves. This works for both endiannesses but in ;; practice is only useful for big-endian. (define_insn_and_split “pred_mov” [(set (match_operand:SVE_STRUCT 0 “aarch64_sve_struct_nonimmediate_operand” “=w, Utx”) (unspec:SVE_STRUCT [(match_operand: 1 “register_operand” “Upl, Upl”) (match_operand:SVE_STRUCT 2 “aarch64_sve_struct_nonimmediate_operand” “Utx, w”)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE && (register_operand (operands[0], mode) || register_operand (operands[2], mode))” “#” “&& reload_completed” [(const_int 0)] { for (unsigned int i = 0; i < <vector_count>; ++i) { rtx subdest = simplify_gen_subreg (mode, operands[0], mode, i * BYTES_PER_SVE_VECTOR); rtx subsrc = simplify_gen_subreg (mode, operands[2], mode, i * BYTES_PER_SVE_VECTOR); aarch64_emit_sve_pred_move (subdest, operands[1], subsrc); } DONE; } [(set_attr “length” “<insn_length>”)] )

(define_expand “mov” [(set (match_operand:PRED_ALL 0 “nonimmediate_operand”) (match_operand:PRED_ALL 1 “general_operand”))] “TARGET_SVE” { if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (mode, operands[1]); } )

(define_insn “*aarch64_sve_mov” [(set (match_operand:PRED_ALL 0 “nonimmediate_operand” “=Upa, m, Upa, Upa, Upa”) (match_operand:PRED_ALL 1 “general_operand” “Upa, Upa, m, Dz, Dm”))] “TARGET_SVE && (register_operand (operands[0], mode) || register_operand (operands[1], mode))” "@ mov\t%0.b, %1.b str\t%1, %0 ldr\t%0, %1 pfalse\t%0.b

return aarch64_output_ptrue (mode, ‘’);" )

;; Handle extractions from a predicate by converting to an integer vector ;; and extracting from there. (define_expand “vec_extract” [(match_operand: 0 “register_operand”) (match_operand: 1 “register_operand”) (match_operand:SI 2 “nonmemory_operand”) ;; Dummy operand to which we can attach the iterator. (reg:SVE_I V0_REGNUM)] “TARGET_SVE” { rtx tmp = gen_reg_rtx (mode); emit_insn (gen_aarch64_sve_dup_const (tmp, operands[1], CONST1_RTX (mode), CONST0_RTX (mode))); emit_insn (gen_vec_extract (operands[0], tmp, operands[2])); DONE; } )

(define_expand “vec_extract” [(set (match_operand: 0 “register_operand”) (vec_select: (match_operand:SVE_ALL 1 “register_operand”) (parallel [(match_operand:SI 2 “nonmemory_operand”)])))] “TARGET_SVE” { poly_int64 val; if (poly_int_rtx_p (operands[2], &val) && known_eq (val, GET_MODE_NUNITS (mode) - 1)) { /* The last element can be extracted with a LASTB and a false predicate. / rtx sel = force_reg (mode, CONST0_RTX (mode)); emit_insn (gen_extract_last_ (operands[0], sel, operands[1])); DONE; } if (!CONST_INT_P (operands[2])) { / Create an index with operand[2] as the base and -1 as the step. It will then be zero for the element we care about. */ rtx index = gen_lowpart (<VEL_INT>mode, operands[2]); index = force_reg (<VEL_INT>mode, index); rtx series = gen_reg_rtx (<V_INT_EQUIV>mode); emit_insn (gen_vec_series<v_int_equiv> (series, index, constm1_rtx));

/* Get a predicate that is true for only that element.  */
rtx zero = CONST0_RTX (<V_INT_EQUIV>mode);
rtx cmp = gen_rtx_EQ (<V_INT_EQUIV>mode, series, zero);
rtx sel = gen_reg_rtx (<VPRED>mode);
emit_insn (gen_vec_cmp<v_int_equiv><vpred> (sel, cmp, series, zero));

/* Select the element using LASTB.  */
emit_insn (gen_extract_last_<mode> (operands[0], sel, operands[1]));
DONE;
  }

} )

;; Extract element zero. This is a special case because we want to force ;; the registers to be the same for the second alternative, and then ;; split the instruction into nothing after RA. (define_insn_and_split “*vec_extract_0” [(set (match_operand: 0 “aarch64_simd_nonimmediate_operand” “=r, w, Utv”) (vec_select: (match_operand:SVE_ALL 1 “register_operand” “w, 0, w”) (parallel [(const_int 0)])))] “TARGET_SVE” { operands[1] = gen_rtx_REG (mode, REGNO (operands[1])); switch (which_alternative) { case 0: return “umov\t%0, %1.[0]”; case 1: return “#”; case 2: return “st1\t{%1.}[0], %0”; default: gcc_unreachable (); } } “&& reload_completed && REG_P (operands[0]) && REGNO (operands[0]) == REGNO (operands[1])” [(const_int 0)] { emit_note (NOTE_INSN_DELETED); DONE; } [(set_attr “type” “neon_to_gp_q, untyped, neon_store1_one_lane_q”)] )

;; Extract an element from the Advanced SIMD portion of the register. ;; We don‘t just reuse the aarch64-simd.md pattern because we don’t ;; want any change in lane number on big-endian targets. (define_insn “*vec_extract_v128” [(set (match_operand: 0 “aarch64_simd_nonimmediate_operand” “=r, w, Utv”) (vec_select: (match_operand:SVE_ALL 1 “register_operand” “w, w, w”) (parallel [(match_operand:SI 2 “const_int_operand”)])))] “TARGET_SVE && IN_RANGE (INTVAL (operands[2]) * GET_MODE_SIZE (mode), 1, 15)” { operands[1] = gen_rtx_REG (mode, REGNO (operands[1])); switch (which_alternative) { case 0: return “umov\t%0, %1.[%2]”; case 1: return “dup\t%0, %1.[%2]”; case 2: return “st1\t{%1.}[%2], %0”; default: gcc_unreachable (); } } [(set_attr “type” “neon_to_gp_q, neon_dup_q, neon_store1_one_lane_q”)] )

;; Extract an element in the range of DUP. This pattern allows the ;; source and destination to be different. (define_insn “*vec_extract_dup” [(set (match_operand: 0 “register_operand” “=w”) (vec_select: (match_operand:SVE_ALL 1 “register_operand” “w”) (parallel [(match_operand:SI 2 “const_int_operand”)])))] “TARGET_SVE && IN_RANGE (INTVAL (operands[2]) * GET_MODE_SIZE (mode), 16, 63)” { operands[0] = gen_rtx_REG (mode, REGNO (operands[0])); return “dup\t%0., %1.[%2]”; } )

;; Extract an element outside the range of DUP. This pattern requires the ;; source and destination to be the same. (define_insn “*vec_extract_ext” [(set (match_operand: 0 “register_operand” “=w”) (vec_select: (match_operand:SVE_ALL 1 “register_operand” “0”) (parallel [(match_operand:SI 2 “const_int_operand”)])))] “TARGET_SVE && INTVAL (operands[2]) * GET_MODE_SIZE (mode) >= 64” { operands[0] = gen_rtx_REG (mode, REGNO (operands[0])); operands[2] = GEN_INT (INTVAL (operands[2]) * GET_MODE_SIZE (mode)); return “ext\t%0.b, %0.b, %0.b, #%2”; } )

;; Extract the last active element of operand 1 into operand 0. ;; If no elements are active, extract the last inactive element instead. (define_insn “extract_last_” [(set (match_operand: 0 “register_operand” “=r, w”) (unspec: [(match_operand: 1 “register_operand” “Upl, Upl”) (match_operand:SVE_ALL 2 “register_operand” “w, w”)] UNSPEC_LASTB))] “TARGET_SVE” “@ lastb\t%0, %1, %2. lastb\t%0, %1, %2.” )

(define_expand “vec_duplicate” [(parallel [(set (match_operand:SVE_ALL 0 “register_operand”) (vec_duplicate:SVE_ALL (match_operand: 1 “aarch64_sve_dup_operand”))) (clobber (scratch:))])] “TARGET_SVE” { if (MEM_P (operands[1])) { rtx ptrue = force_reg (mode, CONSTM1_RTX (mode)); emit_insn (gen_sve_ld1r (operands[0], ptrue, operands[1], CONST0_RTX (mode))); DONE; } } )

;; Accept memory operands for the benefit of combine, and also in case ;; the scalar input gets spilled to memory during RA. We want to split ;; the load at the first opportunity in order to allow the PTRUE to be ;; optimized with surrounding code. (define_insn_and_split “*vec_duplicate_reg” [(set (match_operand:SVE_ALL 0 “register_operand” “=w, w, w”) (vec_duplicate:SVE_ALL (match_operand: 1 “aarch64_sve_dup_operand” “r, w, Uty”))) (clobber (match_scratch: 2 “=X, X, Upl”))] “TARGET_SVE” “@ mov\t%0., %1 mov\t%0., %1 #” “&& MEM_P (operands[1])” [(const_int 0)] { if (GET_CODE (operands[2]) == SCRATCH) operands[2] = gen_reg_rtx (mode); emit_move_insn (operands[2], CONSTM1_RTX (mode)); emit_insn (gen_sve_ld1r (operands[0], operands[2], operands[1], CONST0_RTX (mode))); DONE; } [(set_attr “length” “4,4,8”)] )

;; This is used for vec_duplicates from memory, but can also ;; be used by combine to optimize selects of a a vec_duplicate ;; with zero. (define_insn “sve_ld1r” [(set (match_operand:SVE_ALL 0 “register_operand” “=w”) (unspec:SVE_ALL [(match_operand: 1 “register_operand” “Upl”) (vec_duplicate:SVE_ALL (match_operand: 2 “aarch64_sve_ld1r_operand” “Uty”)) (match_operand:SVE_ALL 3 “aarch64_simd_imm_zero”)] UNSPEC_SEL))] “TARGET_SVE” “ld1r\t%0., %1/z, %2” )

;; Load 128 bits from memory and duplicate to fill a vector. Since there ;; are so few operations on 128-bit “elements”, we don't define a VNx1TI ;; and simply use vectors of bytes instead. (define_insn “*sve_ld1rq” [(set (match_operand:SVE_ALL 0 “register_operand” “=w”) (unspec:SVE_ALL [(match_operand: 1 “register_operand” “Upl”) (match_operand:TI 2 “aarch64_sve_ld1r_operand” “Uty”)] UNSPEC_LD1RQ))] “TARGET_SVE” “ld1rq\t%0., %1/z, %2” )

;; Implement a predicate broadcast by shifting the low bit of the scalar ;; input into the top bit and using a WHILELO. An alternative would be to ;; duplicate the input and do a compare with zero. (define_expand “vec_duplicate” [(set (match_operand:PRED_ALL 0 “register_operand”) (vec_duplicate:PRED_ALL (match_operand 1 “register_operand”)))] “TARGET_SVE” { rtx tmp = gen_reg_rtx (DImode); rtx op1 = gen_lowpart (DImode, operands[1]); emit_insn (gen_ashldi3 (tmp, op1, gen_int_mode (63, DImode))); emit_insn (gen_while_ultdi (operands[0], const0_rtx, tmp)); DONE; } )

(define_insn “vec_series” [(set (match_operand:SVE_I 0 “register_operand” “=w, w, w”) (vec_series:SVE_I (match_operand: 1 “aarch64_sve_index_operand” “Usi, r, r”) (match_operand: 2 “aarch64_sve_index_operand” “r, Usi, r”)))] “TARGET_SVE” “@ index\t%0., #%1, %2 index\t%0., %1, #%2 index\t%0., %1, %2” )

;; Optimize {x, x, x, x, ...} + {0, n, 2n, 3n, ...} if n is in range ;; of an INDEX instruction. (define_insn “*vec_series_plus” [(set (match_operand:SVE_I 0 “register_operand” “=w”) (plus:SVE_I (vec_duplicate:SVE_I (match_operand: 1 “register_operand” “r”)) (match_operand:SVE_I 2 “immediate_operand”)))] “TARGET_SVE && aarch64_check_zero_based_sve_index_immediate (operands[2])” { operands[2] = aarch64_check_zero_based_sve_index_immediate (operands[2]); return “index\t%0., %1, #%2”; } )

;; Unpredicated LD[234]. (define_expand “vec_load_lanes” [(set (match_operand:SVE_STRUCT 0 “register_operand”) (unspec:SVE_STRUCT [(match_dup 2) (match_operand:SVE_STRUCT 1 “memory_operand”)] UNSPEC_LDN))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated LD[234]. (define_insn “vec_mask_load_lanes” [(set (match_operand:SVE_STRUCT 0 “register_operand” “=w”) (unspec:SVE_STRUCT [(match_operand: 2 “register_operand” “Upl”) (match_operand:SVE_STRUCT 1 “memory_operand” “m”)] UNSPEC_LDN))] “TARGET_SVE” “ld<vector_count>\t%0, %2/z, %1” )

;; Unpredicated ST[234]. This is always a full update, so the dependence ;; on the old value of the memory location (via (match_dup 0)) is redundant. ;; There doesn‘t seem to be any obvious benefit to treating the all-true ;; case differently though. In particular, it’s very unlikely that we'll ;; only find out during RTL that a store_lanes is dead. (define_expand “vec_store_lanes” [(set (match_operand:SVE_STRUCT 0 “memory_operand”) (unspec:SVE_STRUCT [(match_dup 2) (match_operand:SVE_STRUCT 1 “register_operand”) (match_dup 0)] UNSPEC_STN))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated ST[234]. (define_insn “vec_mask_store_lanes” [(set (match_operand:SVE_STRUCT 0 “memory_operand” “+m”) (unspec:SVE_STRUCT [(match_operand: 2 “register_operand” “Upl”) (match_operand:SVE_STRUCT 1 “register_operand” “w”) (match_dup 0)] UNSPEC_STN))] “TARGET_SVE” “st<vector_count>\t%1, %2, %0” )

(define_expand “vec_perm” [(match_operand:SVE_ALL 0 “register_operand”) (match_operand:SVE_ALL 1 “register_operand”) (match_operand:SVE_ALL 2 “register_operand”) (match_operand:<V_INT_EQUIV> 3 “aarch64_sve_vec_perm_operand”)] “TARGET_SVE && GET_MODE_NUNITS (mode).is_constant ()” { aarch64_expand_sve_vec_perm (operands[0], operands[1], operands[2], operands[3]); DONE; } )

(define_insn “*aarch64_sve_tbl” [(set (match_operand:SVE_ALL 0 “register_operand” “=w”) (unspec:SVE_ALL [(match_operand:SVE_ALL 1 “register_operand” “w”) (match_operand:<V_INT_EQUIV> 2 “register_operand” “w”)] UNSPEC_TBL))] “TARGET_SVE” “tbl\t%0., %1., %2.” )

(define_insn “*aarch64_sve_<perm_insn><perm_hilo>” [(set (match_operand:PRED_ALL 0 “register_operand” “=Upa”) (unspec:PRED_ALL [(match_operand:PRED_ALL 1 “register_operand” “Upa”) (match_operand:PRED_ALL 2 “register_operand” “Upa”)] PERMUTE))] “TARGET_SVE” “<perm_insn><perm_hilo>\t%0., %1., %2.” )

(define_insn “aarch64_sve_<perm_insn><perm_hilo>” [(set (match_operand:SVE_ALL 0 “register_operand” “=w”) (unspec:SVE_ALL [(match_operand:SVE_ALL 1 “register_operand” “w”) (match_operand:SVE_ALL 2 “register_operand” “w”)] PERMUTE))] “TARGET_SVE” “<perm_insn><perm_hilo>\t%0., %1., %2.” )

(define_insn “*aarch64_sve_rev64” [(set (match_operand:SVE_BHS 0 “register_operand” “=w”) (unspec:SVE_BHS [(match_operand:VNx2BI 1 “register_operand” “Upl”) (unspec:SVE_BHS [(match_operand:SVE_BHS 2 “register_operand” “w”)] UNSPEC_REV64)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “rev\t%0.d, %1/m, %2.d” )

(define_insn “*aarch64_sve_rev32” [(set (match_operand:SVE_BH 0 “register_operand” “=w”) (unspec:SVE_BH [(match_operand:VNx4BI 1 “register_operand” “Upl”) (unspec:SVE_BH [(match_operand:SVE_BH 2 “register_operand” “w”)] UNSPEC_REV32)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “rev\t%0.s, %1/m, %2.s” )

(define_insn “*aarch64_sve_rev16vnx16qi” [(set (match_operand:VNx16QI 0 “register_operand” “=w”) (unspec:VNx16QI [(match_operand:VNx8BI 1 “register_operand” “Upl”) (unspec:VNx16QI [(match_operand:VNx16QI 2 “register_operand” “w”)] UNSPEC_REV16)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “revb\t%0.h, %1/m, %2.h” )

(define_insn “*aarch64_sve_rev” [(set (match_operand:SVE_ALL 0 “register_operand” “=w”) (unspec:SVE_ALL [(match_operand:SVE_ALL 1 “register_operand” “w”)] UNSPEC_REV))] “TARGET_SVE” “rev\t%0., %1.”)

(define_insn “*aarch64_sve_dup_lane” [(set (match_operand:SVE_ALL 0 “register_operand” “=w”) (vec_duplicate:SVE_ALL (vec_select: (match_operand:SVE_ALL 1 “register_operand” “w”) (parallel [(match_operand:SI 2 “const_int_operand”)]))))] “TARGET_SVE && IN_RANGE (INTVAL (operands[2]) * GET_MODE_SIZE (mode), 0, 63)” “dup\t%0., %1.[%2]” )

;; Note that the immediate (third) operand is the lane index not ;; the byte index. (define_insn “*aarch64_sve_ext” [(set (match_operand:SVE_ALL 0 “register_operand” “=w”) (unspec:SVE_ALL [(match_operand:SVE_ALL 1 “register_operand” “0”) (match_operand:SVE_ALL 2 “register_operand” “w”) (match_operand:SI 3 “const_int_operand”)] UNSPEC_EXT))] “TARGET_SVE && IN_RANGE (INTVAL (operands[3]) * GET_MODE_SIZE (mode), 0, 255)” { operands[3] = GEN_INT (INTVAL (operands[3]) * GET_MODE_SIZE (mode)); return “ext\t%0.b, %0.b, %2.b, #%3”; } )

(define_insn “add3” [(set (match_operand:SVE_I 0 “register_operand” “=w, w, w, w”) (plus:SVE_I (match_operand:SVE_I 1 “register_operand” “%0, 0, 0, w”) (match_operand:SVE_I 2 “aarch64_sve_add_operand” “vsa, vsn, vsi, w”)))] “TARGET_SVE” "@ add\t%0., %0., #%D2 sub\t%0., %0., #%N2

return aarch64_output_sve_inc_dec_immediate ("%0.", operands[2]); add\t%0., %1., %2." )

(define_insn “sub3” [(set (match_operand:SVE_I 0 “register_operand” “=w, w”) (minus:SVE_I (match_operand:SVE_I 1 “aarch64_sve_arith_operand” “w, vsa”) (match_operand:SVE_I 2 “register_operand” “w, 0”)))] “TARGET_SVE” “@ sub\t%0., %1., %2. subr\t%0., %0., #%D1” )

;; Unpredicated multiplication. (define_expand “mul3” [(set (match_operand:SVE_I 0 “register_operand”) (unspec:SVE_I [(match_dup 3) (mult:SVE_I (match_operand:SVE_I 1 “register_operand”) (match_operand:SVE_I 2 “aarch64_sve_mul_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Multiplication predicated with a PTRUE. We don‘t actually need the ;; predicate for the first alternative, but using Upa or X isn’t likely ;; to gain much and would make the instruction seem less uniform to the ;; register allocator. (define_insn “*mul3” [(set (match_operand:SVE_I 0 “register_operand” “=w, w”) (unspec:SVE_I [(match_operand: 1 “register_operand” “Upl, Upl”) (mult:SVE_I (match_operand:SVE_I 2 “register_operand” “%0, 0”) (match_operand:SVE_I 3 “aarch64_sve_mul_operand” “vsm, w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “@ mul\t%0., %0., #%3 mul\t%0., %1/m, %0., %3.” )

(define_insn “*madd” [(set (match_operand:SVE_I 0 “register_operand” “=w, w”) (plus:SVE_I (unspec:SVE_I [(match_operand: 1 “register_operand” “Upl, Upl”) (mult:SVE_I (match_operand:SVE_I 2 “register_operand” “%0, w”) (match_operand:SVE_I 3 “register_operand” “w, w”))] UNSPEC_MERGE_PTRUE) (match_operand:SVE_I 4 “register_operand” “w, 0”)))] “TARGET_SVE” “@ mad\t%0., %1/m, %3., %4. mla\t%0., %1/m, %2., %3.” )

(define_insn “*msub3” [(set (match_operand:SVE_I 0 “register_operand” “=w, w”) (minus:SVE_I (match_operand:SVE_I 4 “register_operand” “w, 0”) (unspec:SVE_I [(match_operand: 1 “register_operand” “Upl, Upl”) (mult:SVE_I (match_operand:SVE_I 2 “register_operand” “%0, w”) (match_operand:SVE_I 3 “register_operand” “w, w”))] UNSPEC_MERGE_PTRUE)))] “TARGET_SVE” “@ msb\t%0., %1/m, %3., %4. mls\t%0., %1/m, %2., %3.” )

;; Unpredicated highpart multiplication. (define_expand “mul3_highpart” [(set (match_operand:SVE_I 0 “register_operand”) (unspec:SVE_I [(match_dup 3) (unspec:SVE_I [(match_operand:SVE_I 1 “register_operand”) (match_operand:SVE_I 2 “register_operand”)] MUL_HIGHPART)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated highpart multiplication. (define_insn “*mul3_highpart” [(set (match_operand:SVE_I 0 “register_operand” “=w”) (unspec:SVE_I [(match_operand: 1 “register_operand” “Upl”) (unspec:SVE_I [(match_operand:SVE_I 2 “register_operand” “%0”) (match_operand:SVE_I 3 “register_operand” “w”)] MUL_HIGHPART)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “mulh\t%0., %1/m, %0., %3.” )

;; Unpredicated NEG, NOT and POPCOUNT. (define_expand “2” [(set (match_operand:SVE_I 0 “register_operand”) (unspec:SVE_I [(match_dup 2) (SVE_INT_UNARY:SVE_I (match_operand:SVE_I 1 “register_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; NEG, NOT and POPCOUNT predicated with a PTRUE. (define_insn “*2” [(set (match_operand:SVE_I 0 “register_operand” “=w”) (unspec:SVE_I [(match_operand: 1 “register_operand” “Upl”) (SVE_INT_UNARY:SVE_I (match_operand:SVE_I 2 “register_operand” “w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “<sve_int_op>\t%0., %1/m, %2.” )

;; Vector AND, ORR and XOR. (define_insn “3” [(set (match_operand:SVE_I 0 “register_operand” “=w, w”) (LOGICAL:SVE_I (match_operand:SVE_I 1 “register_operand” “%0, w”) (match_operand:SVE_I 2 “aarch64_sve_logical_operand” “vsl, w”)))] “TARGET_SVE” “@ \t%0., %0., #%C2 \t%0.d, %1.d, %2.d” )

;; Vector AND, ORR and XOR on floating-point modes. We avoid subregs ;; by providing this, but we need to use UNSPECs since rtx logical ops ;; aren't defined for floating-point modes. (define_insn “*3” [(set (match_operand:SVE_F 0 “register_operand” “=w”) (unspec:SVE_F [(match_operand:SVE_F 1 “register_operand” “w”) (match_operand:SVE_F 2 “register_operand” “w”)] LOGICALF))] “TARGET_SVE” “<logicalf_op>\t%0.d, %1.d, %2.d” )

;; REG_EQUAL notes on “not3” should ensure that we can generate ;; this pattern even though the NOT instruction itself is predicated. (define_insn “bic3” [(set (match_operand:SVE_I 0 “register_operand” “=w”) (and:SVE_I (not:SVE_I (match_operand:SVE_I 1 “register_operand” “w”)) (match_operand:SVE_I 2 “register_operand” “w”)))] “TARGET_SVE” “bic\t%0.d, %2.d, %1.d” )

;; Predicate AND. We can reuse one of the inputs as the GP. (define_insn “and3” [(set (match_operand:PRED_ALL 0 “register_operand” “=Upa”) (and:PRED_ALL (match_operand:PRED_ALL 1 “register_operand” “Upa”) (match_operand:PRED_ALL 2 “register_operand” “Upa”)))] “TARGET_SVE” “and\t%0.b, %1/z, %1.b, %2.b” )

;; Unpredicated predicate ORR and XOR. (define_expand “3” [(set (match_operand:PRED_ALL 0 “register_operand”) (and:PRED_ALL (LOGICAL_OR:PRED_ALL (match_operand:PRED_ALL 1 “register_operand”) (match_operand:PRED_ALL 2 “register_operand”)) (match_dup 3)))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated predicate ORR and XOR. (define_insn “pred_3” [(set (match_operand:PRED_ALL 0 “register_operand” “=Upa”) (and:PRED_ALL (LOGICAL:PRED_ALL (match_operand:PRED_ALL 2 “register_operand” “Upa”) (match_operand:PRED_ALL 3 “register_operand” “Upa”)) (match_operand:PRED_ALL 1 “register_operand” “Upa”)))] “TARGET_SVE” “\t%0.b, %1/z, %2.b, %3.b” )

;; Perform a logical operation on operands 2 and 3, using operand 1 as ;; the GP (which is known to be a PTRUE). Store the result in operand 0 ;; and set the flags in the same way as for PTEST. The (and ...) in the ;; UNSPEC_PTEST_PTRUE is logically redundant, but means that the tested ;; value is structurally equivalent to rhs of the second set. (define_insn “*3_cc” [(set (reg:CC CC_REGNUM) (compare:CC (unspec:SI [(match_operand:PRED_ALL 1 “register_operand” “Upa”) (and:PRED_ALL (LOGICAL:PRED_ALL (match_operand:PRED_ALL 2 “register_operand” “Upa”) (match_operand:PRED_ALL 3 “register_operand” “Upa”)) (match_dup 1))] UNSPEC_PTEST_PTRUE) (const_int 0))) (set (match_operand:PRED_ALL 0 “register_operand” “=Upa”) (and:PRED_ALL (LOGICAL:PRED_ALL (match_dup 2) (match_dup 3)) (match_dup 1)))] “TARGET_SVE” “s\t%0.b, %1/z, %2.b, %3.b” )

;; Unpredicated predicate inverse. (define_expand “one_cmpl2” [(set (match_operand:PRED_ALL 0 “register_operand”) (and:PRED_ALL (not:PRED_ALL (match_operand:PRED_ALL 1 “register_operand”)) (match_dup 2)))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated predicate inverse. (define_insn “*one_cmpl3” [(set (match_operand:PRED_ALL 0 “register_operand” “=Upa”) (and:PRED_ALL (not:PRED_ALL (match_operand:PRED_ALL 2 “register_operand” “Upa”)) (match_operand:PRED_ALL 1 “register_operand” “Upa”)))] “TARGET_SVE” “not\t%0.b, %1/z, %2.b” )

;; Predicated predicate BIC and ORN. (define_insn “*3” [(set (match_operand:PRED_ALL 0 “register_operand” “=Upa”) (and:PRED_ALL (NLOGICAL:PRED_ALL (not:PRED_ALL (match_operand:PRED_ALL 2 “register_operand” “Upa”)) (match_operand:PRED_ALL 3 “register_operand” “Upa”)) (match_operand:PRED_ALL 1 “register_operand” “Upa”)))] “TARGET_SVE” “\t%0.b, %1/z, %3.b, %2.b” )

;; Predicated predicate NAND and NOR. (define_insn “*<logical_nn>3” [(set (match_operand:PRED_ALL 0 “register_operand” “=Upa”) (and:PRED_ALL (NLOGICAL:PRED_ALL (not:PRED_ALL (match_operand:PRED_ALL 2 “register_operand” “Upa”)) (not:PRED_ALL (match_operand:PRED_ALL 3 “register_operand” “Upa”))) (match_operand:PRED_ALL 1 “register_operand” “Upa”)))] “TARGET_SVE” “<logical_nn>\t%0.b, %1/z, %2.b, %3.b” )

;; Unpredicated LSL, LSR and ASR by a vector. (define_expand “v3” [(set (match_operand:SVE_I 0 “register_operand”) (unspec:SVE_I [(match_dup 3) (ASHIFT:SVE_I (match_operand:SVE_I 1 “register_operand”) (match_operand:SVE_I 2 “aarch64_sve_shift_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; LSL, LSR and ASR by a vector, predicated with a PTRUE. We don‘t ;; actually need the predicate for the first alternative, but using Upa ;; or X isn’t likely to gain much and would make the instruction seem ;; less uniform to the register allocator. (define_insn “*v3” [(set (match_operand:SVE_I 0 “register_operand” “=w, w”) (unspec:SVE_I [(match_operand: 1 “register_operand” “Upl, Upl”) (ASHIFT:SVE_I (match_operand:SVE_I 2 “register_operand” “w, 0”) (match_operand:SVE_I 3 “aarch64_sve_shift_operand” “D, w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “@ \t%0., %2., #%3 \t%0., %1/m, %0., %3.” )

;; LSL, LSR and ASR by a scalar, which expands into one of the vector ;; shifts above. (define_expand “ASHIFT:optab3” [(set (match_operand:SVE_I 0 “register_operand”) (ASHIFT:SVE_I (match_operand:SVE_I 1 “register_operand”) (match_operand: 2 “general_operand”)))] “TARGET_SVE” { rtx amount; if (CONST_INT_P (operands[2])) { amount = gen_const_vec_duplicate (mode, operands[2]); if (!aarch64_sve_shift_operand (operands[2], mode)) amount = force_reg (mode, amount); } else { amount = gen_reg_rtx (mode); emit_insn (gen_vec_duplicate (amount, convert_to_mode (mode, operands[2], 0))); } emit_insn (gen_v3 (operands[0], operands[1], amount)); DONE; } )

;; Test all bits of operand 1. Operand 0 is a GP that is known to hold PTRUE. ;; ;; Using UNSPEC_PTEST_PTRUE allows combine patterns to assume that the GP ;; is a PTRUE even if the optimizers haven't yet been able to propagate ;; the constant. We would use a separate unspec code for PTESTs involving ;; GPs that might not be PTRUEs. (define_insn “ptest_ptrue” [(set (reg:CC CC_REGNUM) (compare:CC (unspec:SI [(match_operand:PRED_ALL 0 “register_operand” “Upa”) (match_operand:PRED_ALL 1 “register_operand” “Upa”)] UNSPEC_PTEST_PTRUE) (const_int 0)))] “TARGET_SVE” “ptest\t%0, %1.b” )

;; Set element I of the result if operand1 + J < operand2 for all J in [0, I]. ;; with the comparison being unsigned. (define_insn “while_ultGPI:mode<PRED_ALL:mode>” [(set (match_operand:PRED_ALL 0 “register_operand” “=Upa”) (unspec:PRED_ALL [(match_operand:GPI 1 “aarch64_reg_or_zero” “rZ”) (match_operand:GPI 2 “aarch64_reg_or_zero” “rZ”)] UNSPEC_WHILE_LO)) (clobber (reg:CC CC_REGNUM))] “TARGET_SVE” “whilelo\t%0.<PRED_ALL:Vetype>, %1, %2” )

;; WHILELO sets the flags in the same way as a PTEST with a PTRUE GP. ;; Handle the case in which both results are useful. The GP operand ;; to the PTEST isn‘t needed, so we allow it to be anything. (define_insn_and_split “while_ultGPI:mode<PRED_ALL:mode>_cc” [(set (reg:CC CC_REGNUM) (compare:CC (unspec:SI [(match_operand:PRED_ALL 1) (unspec:PRED_ALL [(match_operand:GPI 2 “aarch64_reg_or_zero” “rZ”) (match_operand:GPI 3 “aarch64_reg_or_zero” “rZ”)] UNSPEC_WHILE_LO)] UNSPEC_PTEST_PTRUE) (const_int 0))) (set (match_operand:PRED_ALL 0 “register_operand” “=Upa”) (unspec:PRED_ALL [(match_dup 2) (match_dup 3)] UNSPEC_WHILE_LO))] “TARGET_SVE” “whilelo\t%0.<PRED_ALL:Vetype>, %2, %3” ;; Force the compiler to drop the unused predicate operand, so that we ;; don’t have an unnecessary PTRUE. “&& !CONSTANT_P (operands[1])” [(const_int 0)] { emit_insn (gen_while_ultGPI:mode<PRED_ALL:mode>_cc (operands[0], CONSTM1_RTX (mode), operands[2], operands[3])); DONE; } )

;; Predicated integer comparison. (define_insn “*vec_cmp<cmp_op>_” [(set (match_operand: 0 “register_operand” “=Upa, Upa”) (unspec: [(match_operand: 1 “register_operand” “Upl, Upl”) (match_operand:SVE_I 2 “register_operand” “w, w”) (match_operand:SVE_I 3 “aarch64_sve_cmp_<imm_con>_operand” “<imm_con>, w”)] SVE_COND_INT_CMP)) (clobber (reg:CC CC_REGNUM))] “TARGET_SVE” “@ cmp<cmp_op>\t%0., %1/z, %2., #%3 cmp<cmp_op>\t%0., %1/z, %2., %3.” )

;; Predicated integer comparison in which only the flags result is interesting. (define_insn “*vec_cmp<cmp_op>__ptest” [(set (reg:CC CC_REGNUM) (compare:CC (unspec:SI [(match_operand: 1 “register_operand” “Upl, Upl”) (unspec: [(match_dup 1) (match_operand:SVE_I 2 “register_operand” “w, w”) (match_operand:SVE_I 3 “aarch64_sve_cmp_<imm_con>_operand” “<imm_con>, w”)] SVE_COND_INT_CMP)] UNSPEC_PTEST_PTRUE) (const_int 0))) (clobber (match_scratch: 0 “=Upa, Upa”))] “TARGET_SVE” “@ cmp<cmp_op>\t%0., %1/z, %2., #%3 cmp<cmp_op>\t%0., %1/z, %2., %3.” )

;; Predicated comparison in which both the flag and predicate results ;; are interesting. (define_insn “*vec_cmp<cmp_op>__cc” [(set (reg:CC CC_REGNUM) (compare:CC (unspec:SI [(match_operand: 1 “register_operand” “Upl, Upl”) (unspec: [(match_dup 1) (match_operand:SVE_I 2 “register_operand” “w, w”) (match_operand:SVE_I 3 “aarch64_sve_cmp_<imm_con>_operand” “<imm_con>, w”)] SVE_COND_INT_CMP)] UNSPEC_PTEST_PTRUE) (const_int 0))) (set (match_operand: 0 “register_operand” “=Upa, Upa”) (unspec: [(match_dup 1) (match_dup 2) (match_dup 3)] SVE_COND_INT_CMP))] “TARGET_SVE” “@ cmp<cmp_op>\t%0., %1/z, %2., #%3 cmp<cmp_op>\t%0., %1/z, %2., %3.” )

;; Predicated floating-point comparison (excluding FCMUO, which doesn't ;; allow #0.0 as an operand). (define_insn “*vec_fcm<cmp_op>” [(set (match_operand: 0 “register_operand” “=Upa, Upa”) (unspec: [(match_operand: 1 “register_operand” “Upl, Upl”) (match_operand:SVE_F 2 “register_operand” “w, w”) (match_operand:SVE_F 3 “aarch64_simd_reg_or_zero” “Dz, w”)] SVE_COND_FP_CMP))] “TARGET_SVE” “@ fcm<cmp_op>\t%0., %1/z, %2., #0.0 fcm<cmp_op>\t%0., %1/z, %2., %3.” )

;; Predicated FCMUO. (define_insn “*vec_fcmuo” [(set (match_operand: 0 “register_operand” “=Upa”) (unspec: [(match_operand: 1 “register_operand” “Upl”) (match_operand:SVE_F 2 “register_operand” “w”) (match_operand:SVE_F 3 “register_operand” “w”)] UNSPEC_COND_UO))] “TARGET_SVE” “fcmuo\t%0., %1/z, %2., %3.” )

;; vcond_mask operand order: true, false, mask ;; UNSPEC_SEL operand order: mask, true, false (as for VEC_COND_EXPR) ;; SEL operand order: mask, true, false (define_insn “vcond_mask_” [(set (match_operand:SVE_ALL 0 “register_operand” “=w”) (unspec:SVE_ALL [(match_operand: 3 “register_operand” “Upa”) (match_operand:SVE_ALL 1 “register_operand” “w”) (match_operand:SVE_ALL 2 “register_operand” “w”)] UNSPEC_SEL))] “TARGET_SVE” “sel\t%0., %3, %1., %2.” )

;; Selects between a duplicated immediate and zero. (define_insn “aarch64_sve_dup_const” [(set (match_operand:SVE_I 0 “register_operand” “=w”) (unspec:SVE_I [(match_operand: 1 “register_operand” “Upl”) (match_operand:SVE_I 2 “aarch64_sve_dup_immediate”) (match_operand:SVE_I 3 “aarch64_simd_imm_zero”)] UNSPEC_SEL))] “TARGET_SVE” “mov\t%0., %1/z, #%2” )

;; Integer (signed) vcond. Don't enforce an immediate range here, since it ;; depends on the comparison; leave it to aarch64_expand_sve_vcond instead. (define_expand “vcond<v_int_equiv>” [(set (match_operand:SVE_ALL 0 “register_operand”) (if_then_else:SVE_ALL (match_operator 3 “comparison_operator” [(match_operand:<V_INT_EQUIV> 4 “register_operand”) (match_operand:<V_INT_EQUIV> 5 “nonmemory_operand”)]) (match_operand:SVE_ALL 1 “register_operand”) (match_operand:SVE_ALL 2 “register_operand”)))] “TARGET_SVE” { aarch64_expand_sve_vcond (mode, <V_INT_EQUIV>mode, operands); DONE; } )

;; Integer vcondu. Don't enforce an immediate range here, since it ;; depends on the comparison; leave it to aarch64_expand_sve_vcond instead. (define_expand “vcondu<v_int_equiv>” [(set (match_operand:SVE_ALL 0 “register_operand”) (if_then_else:SVE_ALL (match_operator 3 “comparison_operator” [(match_operand:<V_INT_EQUIV> 4 “register_operand”) (match_operand:<V_INT_EQUIV> 5 “nonmemory_operand”)]) (match_operand:SVE_ALL 1 “register_operand”) (match_operand:SVE_ALL 2 “register_operand”)))] “TARGET_SVE” { aarch64_expand_sve_vcond (mode, <V_INT_EQUIV>mode, operands); DONE; } )

;; Floating-point vcond. All comparisons except FCMUO allow a zero ;; operand; aarch64_expand_sve_vcond handles the case of an FCMUO ;; with zero. (define_expand “vcond<v_fp_equiv>” [(set (match_operand:SVE_SD 0 “register_operand”) (if_then_else:SVE_SD (match_operator 3 “comparison_operator” [(match_operand:<V_FP_EQUIV> 4 “register_operand”) (match_operand:<V_FP_EQUIV> 5 “aarch64_simd_reg_or_zero”)]) (match_operand:SVE_SD 1 “register_operand”) (match_operand:SVE_SD 2 “register_operand”)))] “TARGET_SVE” { aarch64_expand_sve_vcond (mode, <V_FP_EQUIV>mode, operands); DONE; } )

;; Signed integer comparisons. Don't enforce an immediate range here, since ;; it depends on the comparison; leave it to aarch64_expand_sve_vec_cmp_int ;; instead. (define_expand “vec_cmp” [(parallel [(set (match_operand: 0 “register_operand”) (match_operator: 1 “comparison_operator” [(match_operand:SVE_I 2 “register_operand”) (match_operand:SVE_I 3 “nonmemory_operand”)])) (clobber (reg:CC CC_REGNUM))])] “TARGET_SVE” { aarch64_expand_sve_vec_cmp_int (operands[0], GET_CODE (operands[1]), operands[2], operands[3]); DONE; } )

;; Unsigned integer comparisons. Don't enforce an immediate range here, since ;; it depends on the comparison; leave it to aarch64_expand_sve_vec_cmp_int ;; instead. (define_expand “vec_cmpu” [(parallel [(set (match_operand: 0 “register_operand”) (match_operator: 1 “comparison_operator” [(match_operand:SVE_I 2 “register_operand”) (match_operand:SVE_I 3 “nonmemory_operand”)])) (clobber (reg:CC CC_REGNUM))])] “TARGET_SVE” { aarch64_expand_sve_vec_cmp_int (operands[0], GET_CODE (operands[1]), operands[2], operands[3]); DONE; } )

;; Floating-point comparisons. All comparisons except FCMUO allow a zero ;; operand; aarch64_expand_sve_vec_cmp_float handles the case of an FCMUO ;; with zero. (define_expand “vec_cmp” [(set (match_operand: 0 “register_operand”) (match_operator: 1 “comparison_operator” [(match_operand:SVE_F 2 “register_operand”) (match_operand:SVE_F 3 “aarch64_simd_reg_or_zero”)]))] “TARGET_SVE” { aarch64_expand_sve_vec_cmp_float (operands[0], GET_CODE (operands[1]), operands[2], operands[3], false); DONE; } )

;; Branch based on predicate equality or inequality. (define_expand “cbranch4” [(set (pc) (if_then_else (match_operator 0 “aarch64_equality_operator” [(match_operand:PRED_ALL 1 “register_operand”) (match_operand:PRED_ALL 2 “aarch64_simd_reg_or_zero”)]) (label_ref (match_operand 3 "")) (pc)))] "" { rtx ptrue = force_reg (mode, CONSTM1_RTX (mode)); rtx pred; if (operands[2] == CONST0_RTX (mode)) pred = operands[1]; else { pred = gen_reg_rtx (mode); emit_insn (gen_pred_xor3 (pred, ptrue, operands[1], operands[2])); } emit_insn (gen_ptest_ptrue (ptrue, pred)); operands[1] = gen_rtx_REG (CCmode, CC_REGNUM); operands[2] = const0_rtx; } )

;; Unpredicated integer MIN/MAX. (define_expand “3” [(set (match_operand:SVE_I 0 “register_operand”) (unspec:SVE_I [(match_dup 3) (MAXMIN:SVE_I (match_operand:SVE_I 1 “register_operand”) (match_operand:SVE_I 2 “register_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Integer MIN/MAX predicated with a PTRUE. (define_insn “*3” [(set (match_operand:SVE_I 0 “register_operand” “=w”) (unspec:SVE_I [(match_operand: 1 “register_operand” “Upl”) (MAXMIN:SVE_I (match_operand:SVE_I 2 “register_operand” “%0”) (match_operand:SVE_I 3 “register_operand” “w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “\t%0., %1/m, %0., %3.” )

;; Unpredicated floating-point MIN/MAX. (define_expand “3” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 3) (FMAXMIN:SVE_F (match_operand:SVE_F 1 “register_operand”) (match_operand:SVE_F 2 “register_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Floating-point MIN/MAX predicated with a PTRUE. (define_insn “*3” [(set (match_operand:SVE_F 0 “register_operand” “=w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl”) (FMAXMIN:SVE_F (match_operand:SVE_F 2 “register_operand” “%0”) (match_operand:SVE_F 3 “register_operand” “w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “fnm\t%0., %1/m, %0., %3.” )

;; Unpredicated fmin/fmax. (define_expand “<maxmin_uns>3” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 3) (unspec:SVE_F [(match_operand:SVE_F 1 “register_operand”) (match_operand:SVE_F 2 “register_operand”)] FMAXMIN_UNS)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; fmin/fmax predicated with a PTRUE. (define_insn “*<maxmin_uns>3” [(set (match_operand:SVE_F 0 “register_operand” “=w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl”) (unspec:SVE_F [(match_operand:SVE_F 2 “register_operand” “%0”) (match_operand:SVE_F 3 “register_operand” “w”)] FMAXMIN_UNS)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “<maxmin_uns_op>\t%0., %1/m, %0., %3.” )

;; Predicated integer operations. (define_insn “cond_” [(set (match_operand:SVE_I 0 “register_operand” “=w”) (unspec:SVE_I [(match_operand: 1 “register_operand” “Upl”) (match_operand:SVE_I 2 “register_operand” “0”) (match_operand:SVE_I 3 “register_operand” “w”)] SVE_COND_INT_OP))] “TARGET_SVE” “<sve_int_op>\t%0., %1/m, %0., %3.” )

;; Set operand 0 to the last active element in operand 3, or to tied ;; operand 1 if no elements are active. (define_insn “fold_extract_last_” [(set (match_operand: 0 “register_operand” “=r, w”) (unspec: [(match_operand: 1 “register_operand” “0, 0”) (match_operand: 2 “register_operand” “Upl, Upl”) (match_operand:SVE_ALL 3 “register_operand” “w, w”)] UNSPEC_CLASTB))] “TARGET_SVE” “@ clastb\t%0, %2, %0, %3. clastb\t%0, %2, %0, %3.” )

;; Unpredicated integer add reduction. (define_expand “reduc_plus_scal_” [(set (match_operand: 0 “register_operand”) (unspec: [(match_dup 2) (match_operand:SVE_I 1 “register_operand”)] UNSPEC_ADDV))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated integer add reduction. The result is always 64-bits. (define_insn “*reduc_plus_scal_” [(set (match_operand: 0 “register_operand” “=w”) (unspec: [(match_operand: 1 “register_operand” “Upl”) (match_operand:SVE_I 2 “register_operand” “w”)] UNSPEC_ADDV))] “TARGET_SVE” “uaddv\t%d0, %1, %2.” )

;; Unpredicated floating-point add reduction. (define_expand “reduc_plus_scal_” [(set (match_operand: 0 “register_operand”) (unspec: [(match_dup 2) (match_operand:SVE_F 1 “register_operand”)] UNSPEC_FADDV))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated floating-point add reduction. (define_insn “*reduc_plus_scal_” [(set (match_operand: 0 “register_operand” “=w”) (unspec: [(match_operand: 1 “register_operand” “Upl”) (match_operand:SVE_F 2 “register_operand” “w”)] UNSPEC_FADDV))] “TARGET_SVE” “faddv\t%0, %1, %2.” )

;; Unpredicated integer MIN/MAX reduction. (define_expand “reduc_<maxmin_uns>scal” [(set (match_operand: 0 “register_operand”) (unspec: [(match_dup 2) (match_operand:SVE_I 1 “register_operand”)] MAXMINV))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated integer MIN/MAX reduction. (define_insn “*reduc_<maxmin_uns>scal” [(set (match_operand: 0 “register_operand” “=w”) (unspec: [(match_operand: 1 “register_operand” “Upl”) (match_operand:SVE_I 2 “register_operand” “w”)] MAXMINV))] “TARGET_SVE” “<maxmin_uns_op>v\t%0, %1, %2.” )

;; Unpredicated floating-point MIN/MAX reduction. (define_expand “reduc_<maxmin_uns>scal” [(set (match_operand: 0 “register_operand”) (unspec: [(match_dup 2) (match_operand:SVE_F 1 “register_operand”)] FMAXMINV))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Predicated floating-point MIN/MAX reduction. (define_insn “*reduc_<maxmin_uns>scal” [(set (match_operand: 0 “register_operand” “=w”) (unspec: [(match_operand: 1 “register_operand” “Upl”) (match_operand:SVE_F 2 “register_operand” “w”)] FMAXMINV))] “TARGET_SVE” “<maxmin_uns_op>v\t%0, %1, %2.” )

(define_expand “reduc_scal” [(set (match_operand: 0 “register_operand”) (unspec: [(match_dup 2) (match_operand:SVE_I 1 “register_operand”)] BITWISEV))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

(define_insn “*reduc_scal” [(set (match_operand: 0 “register_operand” “=w”) (unspec: [(match_operand: 1 “register_operand” “Upl”) (match_operand:SVE_I 2 “register_operand” “w”)] BITWISEV))] “TARGET_SVE” “<bit_reduc_op>\t%0, %1, %2.” )

;; Unpredicated in-order FP reductions. (define_expand “fold_left_plus_” [(set (match_operand: 0 “register_operand”) (unspec: [(match_dup 3) (match_operand: 1 “register_operand”) (match_operand:SVE_F 2 “register_operand”)] UNSPEC_FADDA))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; In-order FP reductions predicated with PTRUE. (define_insn “*fold_left_plus_” [(set (match_operand: 0 “register_operand” “=w”) (unspec: [(match_operand: 1 “register_operand” “Upl”) (match_operand: 2 “register_operand” “0”) (match_operand:SVE_F 3 “register_operand” “w”)] UNSPEC_FADDA))] “TARGET_SVE” “fadda\t%0, %1, %0, %3.” )

;; Predicated form of the above in-order reduction. (define_insn “*pred_fold_left_plus_” [(set (match_operand: 0 “register_operand” “=w”) (unspec: [(match_operand: 1 “register_operand” “0”) (unspec:SVE_F [(match_operand: 2 “register_operand” “Upl”) (match_operand:SVE_F 3 “register_operand” “w”) (match_operand:SVE_F 4 “aarch64_simd_imm_zero”)] UNSPEC_SEL)] UNSPEC_FADDA))] “TARGET_SVE” “fadda\t%0, %2, %0, %3.” )

;; Unpredicated floating-point addition. (define_expand “add3” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 3) (plus:SVE_F (match_operand:SVE_F 1 “register_operand”) (match_operand:SVE_F 2 “aarch64_sve_float_arith_with_sub_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Floating-point addition predicated with a PTRUE. (define_insn “*add3” [(set (match_operand:SVE_F 0 “register_operand” “=w, w, w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl, Upl, Upl”) (plus:SVE_F (match_operand:SVE_F 2 “register_operand” “%0, 0, w”) (match_operand:SVE_F 3 “aarch64_sve_float_arith_with_sub_operand” “vsA, vsN, w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “@ fadd\t%0., %1/m, %0., #%3 fsub\t%0., %1/m, %0., #%N3 fadd\t%0., %2., %3.” )

;; Unpredicated floating-point subtraction. (define_expand “sub3” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 3) (minus:SVE_F (match_operand:SVE_F 1 “aarch64_sve_float_arith_operand”) (match_operand:SVE_F 2 “register_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Floating-point subtraction predicated with a PTRUE. (define_insn “*sub3” [(set (match_operand:SVE_F 0 “register_operand” “=w, w, w, w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl, Upl, Upl, Upl”) (minus:SVE_F (match_operand:SVE_F 2 “aarch64_sve_float_arith_operand” “0, 0, vsA, w”) (match_operand:SVE_F 3 “aarch64_sve_float_arith_with_sub_operand” “vsA, vsN, 0, w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE && (register_operand (operands[2], mode) || register_operand (operands[3], mode))” “@ fsub\t%0., %1/m, %0., #%3 fadd\t%0., %1/m, %0., #%N3 fsubr\t%0., %1/m, %0., #%2 fsub\t%0., %2., %3.” )

;; Unpredicated floating-point multiplication. (define_expand “mul3” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 3) (mult:SVE_F (match_operand:SVE_F 1 “register_operand”) (match_operand:SVE_F 2 “aarch64_sve_float_mul_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Floating-point multiplication predicated with a PTRUE. (define_insn “*mul3” [(set (match_operand:SVE_F 0 “register_operand” “=w, w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl, Upl”) (mult:SVE_F (match_operand:SVE_F 2 “register_operand” “%0, w”) (match_operand:SVE_F 3 “aarch64_sve_float_mul_operand” “vsM, w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “@ fmul\t%0., %1/m, %0., #%3 fmul\t%0., %2., %3.” )

;; Unpredicated fma (%0 = (%1 * %2) + %3). (define_expand “fma4” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 4) (fma:SVE_F (match_operand:SVE_F 1 “register_operand”) (match_operand:SVE_F 2 “register_operand”) (match_operand:SVE_F 3 “register_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[4] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; fma predicated with a PTRUE. (define_insn “*fma4” [(set (match_operand:SVE_F 0 “register_operand” “=w, w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl, Upl”) (fma:SVE_F (match_operand:SVE_F 3 “register_operand” “%0, w”) (match_operand:SVE_F 4 “register_operand” “w, w”) (match_operand:SVE_F 2 “register_operand” “w, 0”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “@ fmad\t%0., %1/m, %4., %2. fmla\t%0., %1/m, %3., %4.” )

;; Unpredicated fnma (%0 = (-%1 * %2) + %3). (define_expand “fnma4” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 4) (fma:SVE_F (neg:SVE_F (match_operand:SVE_F 1 “register_operand”)) (match_operand:SVE_F 2 “register_operand”) (match_operand:SVE_F 3 “register_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[4] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; fnma predicated with a PTRUE. (define_insn “*fnma4” [(set (match_operand:SVE_F 0 “register_operand” “=w, w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl, Upl”) (fma:SVE_F (neg:SVE_F (match_operand:SVE_F 3 “register_operand” “%0, w”)) (match_operand:SVE_F 4 “register_operand” “w, w”) (match_operand:SVE_F 2 “register_operand” “w, 0”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “@ fmsb\t%0., %1/m, %4., %2. fmls\t%0., %1/m, %3., %4.” )

;; Unpredicated fms (%0 = (%1 * %2) - %3). (define_expand “fms4” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 4) (fma:SVE_F (match_operand:SVE_F 1 “register_operand”) (match_operand:SVE_F 2 “register_operand”) (neg:SVE_F (match_operand:SVE_F 3 “register_operand”)))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[4] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; fms predicated with a PTRUE. (define_insn “*fms4” [(set (match_operand:SVE_F 0 “register_operand” “=w, w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl, Upl”) (fma:SVE_F (match_operand:SVE_F 3 “register_operand” “%0, w”) (match_operand:SVE_F 4 “register_operand” “w, w”) (neg:SVE_F (match_operand:SVE_F 2 “register_operand” “w, 0”)))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “@ fnmsb\t%0., %1/m, %4., %2. fnmls\t%0., %1/m, %3., %4.” )

;; Unpredicated fnms (%0 = (-%1 * %2) - %3). (define_expand “fnms4” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 4) (fma:SVE_F (neg:SVE_F (match_operand:SVE_F 1 “register_operand”)) (match_operand:SVE_F 2 “register_operand”) (neg:SVE_F (match_operand:SVE_F 3 “register_operand”)))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[4] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; fnms predicated with a PTRUE. (define_insn “*fnms4” [(set (match_operand:SVE_F 0 “register_operand” “=w, w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl, Upl”) (fma:SVE_F (neg:SVE_F (match_operand:SVE_F 3 “register_operand” “%0, w”)) (match_operand:SVE_F 4 “register_operand” “w, w”) (neg:SVE_F (match_operand:SVE_F 2 “register_operand” “w, 0”)))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “@ fnmad\t%0., %1/m, %4., %2. fnmla\t%0., %1/m, %3., %4.” )

;; Unpredicated floating-point division. (define_expand “div3” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 3) (div:SVE_F (match_operand:SVE_F 1 “register_operand”) (match_operand:SVE_F 2 “register_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[3] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Floating-point division predicated with a PTRUE. (define_insn “*div3” [(set (match_operand:SVE_F 0 “register_operand” “=w, w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl, Upl”) (div:SVE_F (match_operand:SVE_F 2 “register_operand” “0, w”) (match_operand:SVE_F 3 “register_operand” “w, 0”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “@ fdiv\t%0., %1/m, %0., %3. fdivr\t%0., %1/m, %0., %2.” )

;; Unpredicated FNEG, FABS and FSQRT. (define_expand “2” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 2) (SVE_FP_UNARY:SVE_F (match_operand:SVE_F 1 “register_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; FNEG, FABS and FSQRT predicated with a PTRUE. (define_insn “*2” [(set (match_operand:SVE_F 0 “register_operand” “=w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl”) (SVE_FP_UNARY:SVE_F (match_operand:SVE_F 2 “register_operand” “w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “<sve_fp_op>\t%0., %1/m, %2.” )

;; Unpredicated FRINTy. (define_expand “<frint_pattern>2” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 2) (unspec:SVE_F [(match_operand:SVE_F 1 “register_operand”)] FRINT)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; FRINTy predicated with a PTRUE. (define_insn “*<frint_pattern>2” [(set (match_operand:SVE_F 0 “register_operand” “=w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl”) (unspec:SVE_F [(match_operand:SVE_F 2 “register_operand” “w”)] FRINT)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “frint<frint_suffix>\t%0., %1/m, %2.” )

;; Unpredicated conversion of floats to integers of the same size (HF to HI, ;; SF to SI or DF to DI). (define_expand “<fix_trunc_optab><v_int_equiv>2” [(set (match_operand:<V_INT_EQUIV> 0 “register_operand”) (unspec:<V_INT_EQUIV> [(match_dup 2) (FIXUORS:<V_INT_EQUIV> (match_operand:SVE_F 1 “register_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Conversion of SF to DI, SI or HI, predicated with a PTRUE. (define_insn “*<fix_trunc_optab>v16hsf2” [(set (match_operand:SVE_HSDI 0 “register_operand” “=w”) (unspec:SVE_HSDI [(match_operand: 1 “register_operand” “Upl”) (FIXUORS:SVE_HSDI (match_operand:VNx8HF 2 “register_operand” “w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “fcvtz\t%0., %1/m, %2.h” )

;; Conversion of SF to DI or SI, predicated with a PTRUE. (define_insn “*<fix_trunc_optab>vnx4sf2” [(set (match_operand:SVE_SDI 0 “register_operand” “=w”) (unspec:SVE_SDI [(match_operand: 1 “register_operand” “Upl”) (FIXUORS:SVE_SDI (match_operand:VNx4SF 2 “register_operand” “w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “fcvtz\t%0., %1/m, %2.s” )

;; Conversion of DF to DI or SI, predicated with a PTRUE. (define_insn “*<fix_trunc_optab>vnx2df2” [(set (match_operand:SVE_SDI 0 “register_operand” “=w”) (unspec:SVE_SDI [(match_operand:VNx2BI 1 “register_operand” “Upl”) (FIXUORS:SVE_SDI (match_operand:VNx2DF 2 “register_operand” “w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “fcvtz\t%0., %1/m, %2.d” )

;; Unpredicated conversion of integers to floats of the same size ;; (HI to HF, SI to SF or DI to DF). (define_expand “<v_int_equiv>2” [(set (match_operand:SVE_F 0 “register_operand”) (unspec:SVE_F [(match_dup 2) (FLOATUORS:SVE_F (match_operand:<V_INT_EQUIV> 1 “register_operand”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” { operands[2] = force_reg (mode, CONSTM1_RTX (mode)); } )

;; Conversion of DI, SI or HI to the same number of HFs, predicated ;; with a PTRUE. (define_insn “*vnx8hf2” [(set (match_operand:VNx8HF 0 “register_operand” “=w”) (unspec:VNx8HF [(match_operand: 1 “register_operand” “Upl”) (FLOATUORS:VNx8HF (match_operand:SVE_HSDI 2 “register_operand” “w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “<su_optab>cvtf\t%0.h, %1/m, %2.” )

;; Conversion of DI or SI to the same number of SFs, predicated with a PTRUE. (define_insn “*vnx4sf2” [(set (match_operand:VNx4SF 0 “register_operand” “=w”) (unspec:VNx4SF [(match_operand: 1 “register_operand” “Upl”) (FLOATUORS:VNx4SF (match_operand:SVE_SDI 2 “register_operand” “w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “<su_optab>cvtf\t%0.s, %1/m, %2.” )

;; Conversion of DI or SI to DF, predicated with a PTRUE. (define_insn “aarch64_sve_vnx2df2” [(set (match_operand:VNx2DF 0 “register_operand” “=w”) (unspec:VNx2DF [(match_operand:VNx2BI 1 “register_operand” “Upl”) (FLOATUORS:VNx2DF (match_operand:SVE_SDI 2 “register_operand” “w”))] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “<su_optab>cvtf\t%0.d, %1/m, %2.” )

;; Conversion of DFs to the same number of SFs, or SFs to the same number ;; of HFs. (define_insn “*trunc2” [(set (match_operand:SVE_HSF 0 “register_operand” “=w”) (unspec:SVE_HSF [(match_operand:<VWIDE_PRED> 1 “register_operand” “Upl”) (unspec:SVE_HSF [(match_operand: 2 “register_operand” “w”)] UNSPEC_FLOAT_CONVERT)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “fcvt\t%0., %1/m, %2.” )

;; Conversion of SFs to the same number of DFs, or HFs to the same number ;; of SFs. (define_insn “aarch64_sve_extend2” [(set (match_operand: 0 “register_operand” “=w”) (unspec: [(match_operand:<VWIDE_PRED> 1 “register_operand” “Upl”) (unspec: [(match_operand:SVE_HSF 2 “register_operand” “w”)] UNSPEC_FLOAT_CONVERT)] UNSPEC_MERGE_PTRUE))] “TARGET_SVE” “fcvt\t%0., %1/m, %2.” )

;; Unpack the low or high half of a predicate, where “high” refers to ;; the low-numbered lanes for big-endian and the high-numbered lanes ;; for little-endian. (define_expand “vec_unpack<perm_hilo>” [(match_operand: 0 “register_operand”) (unspec: [(match_operand:PRED_BHS 1 “register_operand”)] UNPACK)] “TARGET_SVE” { emit_insn ((<hi_lanes_optab> ? gen_aarch64_sve_punpkhi_<PRED_BHS:mode> : gen_aarch64_sve_punpklo_<PRED_BHS:mode>) (operands[0], operands[1])); DONE; } )

;; PUNPKHI and PUNPKLO. (define_insn “aarch64_sve_punpk<perm_hilo>_” [(set (match_operand: 0 “register_operand” “=Upa”) (unspec: [(match_operand:PRED_BHS 1 “register_operand” “Upa”)] UNPACK_UNSIGNED))] “TARGET_SVE” “punpk<perm_hilo>\t%0.h, %1.b” )

;; Unpack the low or high half of a vector, where “high” refers to ;; the low-numbered lanes for big-endian and the high-numbered lanes ;; for little-endian. (define_expand “vec_unpack<perm_hilo><SVE_BHSI:mode>” [(match_operand: 0 “register_operand”) (unspec: [(match_operand:SVE_BHSI 1 “register_operand”)] UNPACK)] “TARGET_SVE” { emit_insn ((<hi_lanes_optab> ? gen_aarch64_sve_unpkhi_<SVE_BHSI:mode> : gen_aarch64_sve_unpklo_<SVE_BHSI:mode>) (operands[0], operands[1])); DONE; } )

;; SUNPKHI, UUNPKHI, SUNPKLO and UUNPKLO. (define_insn “aarch64_sve_unpk<perm_hilo>_<SVE_BHSI:mode>” [(set (match_operand: 0 “register_operand” “=w”) (unspec: [(match_operand:SVE_BHSI 1 “register_operand” “w”)] UNPACK))] “TARGET_SVE” “unpk<perm_hilo>\t%0., %1.” )

;; Unpack one half of a VNx4SF to VNx2DF, or one half of a VNx8HF to VNx4SF. ;; First unpack the source without conversion, then float-convert the ;; unpacked source. (define_expand “vec_unpacks_<perm_hilo>_” [(match_operand: 0 “register_operand”) (unspec:SVE_HSF [(match_operand:SVE_HSF 1 “register_operand”)] UNPACK_UNSIGNED)] “TARGET_SVE” { /* Use ZIP to do the unpack, since we don't care about the upper halves and since it has the nice property of not needing any subregs. If using UUNPK* turns out to be preferable, we could model it as a ZIP whose first operand is zero. */ rtx temp = gen_reg_rtx (mode); emit_insn ((<hi_lanes_optab> ? gen_aarch64_sve_zip2 : gen_aarch64_sve_zip1) (temp, operands[1], operands[1])); rtx ptrue = force_reg (<VWIDE_PRED>mode, CONSTM1_RTX (<VWIDE_PRED>mode)); emit_insn (gen_aarch64_sve_extend2 (operands[0], ptrue, temp)); DONE; } )

;; Unpack one half of a VNx4SI to VNx2DF. First unpack from VNx4SI ;; to VNx2DI, reinterpret the VNx2DI as a VNx4SI, then convert the ;; unpacked VNx4SI to VNx2DF. (define_expand “vec_unpack<su_optab>float<perm_hilo>_vnx4si” [(match_operand:VNx2DF 0 “register_operand”) (FLOATUORS:VNx2DF (unspec:VNx2DI [(match_operand:VNx4SI 1 “register_operand”)] UNPACK_UNSIGNED))] “TARGET_SVE” { /* Use ZIP to do the unpack, since we don't care about the upper halves and since it has the nice property of not needing any subregs. If using UUNPK* turns out to be preferable, we could model it as a ZIP whose first operand is zero. */ rtx temp = gen_reg_rtx (VNx4SImode); emit_insn ((<hi_lanes_optab> ? gen_aarch64_sve_zip2vnx4si : gen_aarch64_sve_zip1vnx4si) (temp, operands[1], operands[1])); rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode)); emit_insn (gen_aarch64_sve_FLOATUORS:optabvnx4sivnx2df2 (operands[0], ptrue, temp)); DONE; } )

;; Predicate pack. Use UZP1 on the narrower type, which discards ;; the high part of each wide element. (define_insn “vec_pack_trunc_” [(set (match_operand:PRED_BHS 0 “register_operand” “=Upa”) (unspec:PRED_BHS [(match_operand: 1 “register_operand” “Upa”) (match_operand: 2 “register_operand” “Upa”)] UNSPEC_PACK))] “TARGET_SVE” “uzp1\t%0., %1., %2.” )

;; Integer pack. Use UZP1 on the narrower type, which discards ;; the high part of each wide element. (define_insn “vec_pack_trunc_” [(set (match_operand:SVE_BHSI 0 “register_operand” “=w”) (unspec:SVE_BHSI [(match_operand: 1 “register_operand” “w”) (match_operand: 2 “register_operand” “w”)] UNSPEC_PACK))] “TARGET_SVE” “uzp1\t%0., %1., %2.” )

;; Convert two vectors of DF to SF, or two vectors of SF to HF, and pack ;; the results into a single vector. (define_expand “vec_pack_trunc_” [(set (match_dup 4) (unspec:SVE_HSF [(match_dup 3) (unspec:SVE_HSF [(match_operand: 1 “register_operand”)] UNSPEC_FLOAT_CONVERT)] UNSPEC_MERGE_PTRUE)) (set (match_dup 5) (unspec:SVE_HSF [(match_dup 3) (unspec:SVE_HSF [(match_operand: 2 “register_operand”)] UNSPEC_FLOAT_CONVERT)] UNSPEC_MERGE_PTRUE)) (set (match_operand:SVE_HSF 0 “register_operand”) (unspec:SVE_HSF [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))] “TARGET_SVE” { operands[3] = force_reg (<VWIDE_PRED>mode, CONSTM1_RTX (<VWIDE_PRED>mode)); operands[4] = gen_reg_rtx (mode); operands[5] = gen_reg_rtx (mode); } )

;; Convert two vectors of DF to SI and pack the results into a single vector. (define_expand “vec_pack_fix_trunc_vnx2df” [(set (match_dup 4) (unspec:VNx4SI [(match_dup 3) (FIXUORS:VNx4SI (match_operand:VNx2DF 1 “register_operand”))] UNSPEC_MERGE_PTRUE)) (set (match_dup 5) (unspec:VNx4SI [(match_dup 3) (FIXUORS:VNx4SI (match_operand:VNx2DF 2 “register_operand”))] UNSPEC_MERGE_PTRUE)) (set (match_operand:VNx4SI 0 “register_operand”) (unspec:VNx4SI [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))] “TARGET_SVE” { operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode)); operands[4] = gen_reg_rtx (VNx4SImode); operands[5] = gen_reg_rtx (VNx4SImode); } )

;; Predicated floating-point operations. (define_insn “cond_” [(set (match_operand:SVE_F 0 “register_operand” “=w”) (unspec:SVE_F [(match_operand: 1 “register_operand” “Upl”) (match_operand:SVE_F 2 “register_operand” “0”) (match_operand:SVE_F 3 “register_operand” “w”)] SVE_COND_FP_OP))] “TARGET_SVE” “<sve_fp_op>\t%0., %1/m, %0., %3.” )

;; Shift an SVE vector left and insert a scalar into element 0. (define_insn “vec_shl_insert_” [(set (match_operand:SVE_ALL 0 “register_operand” “=w, w”) (unspec:SVE_ALL [(match_operand:SVE_ALL 1 “register_operand” “0, 0”) (match_operand: 2 “register_operand” “rZ, w”)] UNSPEC_INSR))] “TARGET_SVE” “@ insr\t%0., %2 insr\t%0., %2” )