)]}'
{
  "commit": "413d90e7515b571bbbf33475695ba042cf5890a6",
  "tree": "e0c746badc5b7453d58394e2abb71fcf84b8cd8f",
  "parents": [
    "deacdfca7059dbec496a78a2727dfe9efd9ba71d"
  ],
  "author": {
    "name": "Jim Lin",
    "email": "jim@andestech.com",
    "time": "Mon Jul 06 09:37:25 2026 -0600"
  },
  "committer": {
    "name": "Jeff Law",
    "email": "jeffrey.law@oss.qualcomm.com",
    "time": "Mon Jul 06 09:37:50 2026 -0600"
  },
  "message": "[PATCH] RISC-V: Skip shift-shift-7.c under -Og\n\nAt -Og the a \u003c\u003c 1 is kept as a separate slliw instead of being folded\ninto the zero_extendsidi2_shifted sequence, so the \"slli\" regex matches\nboth slliw and slli and the scan-assembler-times \"slli\" 1 check fails.\nSkip the test under -Og.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/shift-shift-7.c: Skip under -Og.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3ecd9ebdc39c5dae43de42b77644db3a58d88a6c",
      "old_mode": 33188,
      "old_path": "gcc/testsuite/gcc.target/riscv/shift-shift-7.c",
      "new_id": "8fe9143960e61bbe17a08889254b660155de4757",
      "new_mode": 33188,
      "new_path": "gcc/testsuite/gcc.target/riscv/shift-shift-7.c"
    }
  ]
}