)]}'
{
  "commit": "4157d433df1ccc30ca2db2e4e9448318d730299f",
  "tree": "78f3b723e2e4d0847fa5c4ddc301ac2a9ca7f718",
  "parents": [
    "762ca0be09e00d02a72bd65fe8c3027a056d4a81"
  ],
  "author": {
    "name": "Jeff Law",
    "email": "jlaw@ventanamicro.com",
    "time": "Sat Jun 21 08:24:58 2025 -0600"
  },
  "committer": {
    "name": "Jeff Law",
    "email": "jlaw@ventanamicro.com",
    "time": "Mon Jul 14 06:41:16 2025 -0600"
  },
  "message": "[RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V\n\nThe RISC-V prefetch support is broken in a few ways.  This addresses the data\nside prefetch problems.  I\u0027d mistakenly thought this BZ was a prefetch.i\nrelated (which has deeper problems).\n\nThe basic problem is we were accepting any valid address when in fact there are\nrestrictions.  This patch more precisely defines the predicate such that we\nallow\n\nREG\nREG+D\n\nWhere D must have the low 5 bits clear.  Note that absolute addresses fall into\nthe REG+D form using the x0 for the register operand since it always has the\nvalue zero.  The test verifies REG, REG+D, ABS addressing modes that are valid\nas well as REG+D and ABS which must be reloaded into a REG because the\ndisplacement has low bits set.\n\nAn earlier version of this patch has gone through testing in my tester on rv32\nand rv64.  Obviously I\u0027ll wait for pre-commit CI to do its thing before moving\nforward.\n\nThis is a good backport candidate after simmering on the trunk for a bit.\n\n\tPR target/118241\ngcc/\n\t* config/riscv/predicates.md (prefetch_operand): New predicate.\n\t* config/riscv/constraints.md (Q): New constraint.\n\t* config/riscv/riscv.md (prefetch): Use new predicate and constraint.\n\t(riscv_prefetchi_\u003cmode\u003e): Similarly.\n\ngcc/testsuite/\n\t* gcc.target/riscv/pr118241.c: New test.\n\n(cherry picked from commit 49199bb29628365fc6c60bd185808a1bad65086d)\n",
  "tree_diff": [
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