tree 1d87c2de420d758d05e8195ad5a0825c0749a69a
parent 2473f28d79c480192aba783a08de8b0285c08213
author Philipp Tomsich <philipp.tomsich@vrull.eu> 1669031063 +0100
committer Philipp Tomsich <philipp.tomsich@vrull.eu> 1669031625 +0100

RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero

With the recent improvements to the splitting of special cases of
branch patterns on RISC-V, a dependency on an unmerged/in-discussion
change for branch-equals-zero slipped in: this allowed a non-X mode to
be presented to branch-equals-zero (where only X mode is permissible).

This addresses the issue by wrapping the ANYI operand in a paradoxical
SUBREG:X (the high bits can be safely ignored, as we we perform an
and-immediate before the branch in the pattern).

Tested against the GCC testsuite and committed as obvious.

gcc/ChangeLog:

	PR target/107786
	* config/riscv/riscv.md
	(*branch<ANYI:mode>_shiftedarith_equals_zero): Wrap ANYI
	in a subreg, as our branch instructions only supports X.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/pr107786-2.c: New test.
	* gcc.target/riscv/pr107786.c: New test.