)]}'
{
  "commit": "592dc08e0509bab1dc786db1699f197e5f0fdcea",
  "tree": "0ea6c92c7b19915d093ab662eb983e1d09790624",
  "parents": [
    "d564198f960a2f5994dde3f6b83d7a62021e49c3"
  ],
  "author": {
    "name": "Kong Lingling",
    "email": "lingling.kong@intel.com",
    "time": "Wed Jan 18 17:52:52 2023 +0800"
  },
  "committer": {
    "name": "Hongyu Wang",
    "email": "hongyu.wang@intel.com",
    "time": "Thu Dec 07 09:31:13 2023 +0800"
  },
  "message": "[APX NDD] Support APX NDD for adc insns\n\nLegacy adc patterns are commonly adopted to TImode add, when extending TImode\nadd to NDD version, operands[0] and operands[1] can be different, so extra move\nshould be emitted if those patterns have optimization when adding const0_rtx.\n\nFor TImode insn, there could be register overlapping between operands[0]\nand operands[1] as x86 allocates TImode register sequentially like rax:rdi,\nrdi:rdx. After postreload split for TImode, write to 1st highpart rdi will\nbe overrided by the 2nd lowpart rdi if 2nd lowpart rdi have different src as\ninput, then the write to 1st highpart rdi will missed and cause miscompliation.\nIn addition, when input operands contain memory, the address register may also\noverlaps with dest register if it is marked dead after one of highpart/lowpart\noperation was done.\nSo the earlyclobber modifier \u0027\u0026\u0027 should be added to NDD dest to avoid\noverlapping between dest and src operands.\n\nNDD instructions will automatically zero-extend dest register to 64bit, so for\nzext patterns it can adopt all NDD form that have memory src input.\n\ngcc/ChangeLog:\n\n\t* config/i386/i386.md (*add\u003cdwi\u003e3_doubleword): Add ndd alternatives,\n\tadopt \u0027\u0026\u0027 to ndd dest and move operands[1] to operands[0] when they are\n\tnot equal.\n\t(*add\u003cdwi\u003e3_doubleword_cc_overflow_1): Likewise.\n\t(*addv\u003cdwi\u003e4_doubleword): Likewise.\n\t(*addv\u003cdwi\u003e4_doubleword_1): Likewise.\n\t(*add\u003cdwi\u003e3_doubleword_zext): Likewise.\n\t(addv\u003cmode\u003e4_overflow_1): Add ndd alternatives.\n\t(*addv\u003cmode\u003e4_overflow_2): Likewise.\n\t(@add\u003cmode\u003e3_carry): Likewise.\n\t(*add\u003cmode\u003e3_carry_0): Likewise.\n\t(*addsi3_carry_zext): Likewise.\n\t(addcarry\u003cmode\u003e): Likewise.\n\t(addcarry\u003cmode\u003e_0): Likewise.\n\t(*addcarry\u003cmode\u003e_1): Likewise.\n\t(*add\u003cmode\u003e3_eq): Likewise.\n\t(*add\u003cmode\u003e3_ne): Likewise.\n\t(*addsi3_carry_zext_0): Likewise, and use nonimmediate_operand for\n\toperands[1] to accept memory input for NDD alternative.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/i386/apx-ndd-adc.c: New test.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a16261212278eee5ccef6b8ee71fe61552a93c5e",
      "old_mode": 33188,
      "old_path": "gcc/config/i386/i386.md",
      "new_id": "8dd8216041e196f8a039d1cebf45864467f3cf69",
      "new_mode": 33188,
      "new_path": "gcc/config/i386/i386.md"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "9d5991457da7d2932d5e90d966c265d0281b01da",
      "new_mode": 33188,
      "new_path": "gcc/testsuite/gcc.target/i386/apx-ndd-adc.c"
    }
  ]
}