| commit | 62eb400b51f8a552320a250b3ac0b5d2ebd8927f | [log] [tgz] |
|---|---|---|
| author | Richard Earnshaw <rearnsha@arm.com> | Thu Jan 20 15:41:37 2022 +0000 |
| committer | Richard Earnshaw <rearnsha@arm.com> | Thu Jan 20 15:44:11 2022 +0000 |
| tree | 63f78cd4674250bd5b2af93c3db9028615d545b6 | |
| parent | 6b73c07ec2e836a5cf7bacd6c7257fb8512c681e [diff] |
aarch64: allow ld1/stq in test output [PR102517] Following the changes to the inline memcpy operations get expanded, we now generate ld1/st1 using a 128-bit vector register rather than ldp with Q registers. The behaviour is equivalent, so relax the tests to permit either variant. gcc/testsuite/ChangeLog: PR target/102517 * gcc.target/aarch64/cpymem-q-reg_1.c: Allow ld1 and st1 for the memcpy expansion.