)]}'
{
  "commit": "63fa52f94b89eefb8d56829d53bb8a59015f0bb6",
  "tree": "88602da4e90ca91d6a4a9d994232fdea45d6799d",
  "parents": [
    "313ca57ed380ac037fbbce6124af070a7bd27cb6"
  ],
  "author": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Wed Sep 02 13:07:25 2026 +0800"
  },
  "committer": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Fri Sep 04 09:49:49 2026 +0800"
  },
  "message": "RISC-V: Allow RVV register overlap for vwmaccu.vx undef\n\nLike vwmacc[u].vx, allow the rvv register overlap for the undef\nform of the dual widen ternary vx insn vwmaccu.vx.  The undef form\ncomes from the combine of the vec_duplicate and the vwmaccu.vv\ninstead of the intrinsic.  After that, all the dual widen ternary\nvx insns are able to overlap.\n\ngcc/ChangeLog:\n\n\t* config/riscv/vector.md: Leverage Wvr constraint.\n\nSigned-off-by: Pan Li \u003cpan2.li@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "bbdbe8eddd1d8933ffabb2ab9df8f0aa8c13ab41",
      "old_mode": 33188,
      "old_path": "gcc/config/riscv/vector.md",
      "new_id": "e760f708faf29daa2aa7d9b10bd834f8a7b716c5",
      "new_mode": 33188,
      "new_path": "gcc/config/riscv/vector.md"
    }
  ]
}