)]}'
{
  "commit": "6924bcee14bdcecf0fcb6764f546dd7ca8ca8f9a",
  "tree": "ab810eba2273cba2a441c6ebcb7d351ddbc3299e",
  "parents": [
    "be7393903c28328a6d2dfd5bbd6347fcbf767bec"
  ],
  "author": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Sat Sep 12 16:00:30 2026 +0800"
  },
  "committer": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Fri Sep 18 14:27:59 2026 +0800"
  },
  "message": "RISC-V: Fix reg overlap for vs1 of the widening integer reduction\n\nThe vs1 of the widening reduction (aka vwredsum[u].vs) is read with\nEEW \u003d 2 * SEW while the vs2 is read with EEW \u003d SEW.  The section 5.2\nof the vector spec reserves any encoding in which one vector register\nsupplies source operands with two or more different EEWs.  Thus, the\nvs1 must not fall inside the vs2 register group, but we may have below\nasm dump when the vs1 comes from the vs2 register group.\n\n  vwredsum.vs v2,v2,v3\n\nAdd one new constraint Wn3 which indicates the register of the operand\ndoesn\u0027t overlap the register group of the operand 3 (aka vs2), and then\ntake it for the operand 4 (aka vs1) of the widening integer reduction.\nSee below issue of the riscv-isa-manual for more details.\n\n  https://github.com/riscv/riscv-isa-manual/issues/2350\n\ngcc/ChangeLog:\n\n\t* config/riscv/constraints.md (Wn3): New constraint for the\n\tvector register which doesn\u0027t overlap the register group of\n\tthe operand 3.\n\t* config/riscv/riscv-protos.h (riscv_v_widen_non_overlap_constraint_ok):\n\tNew function declaration.\n\t* config/riscv/riscv-v.cc (riscv_v_reg_group_overlap_p): New\n\tfunction to tell if two vector register groups overlap.\n\t(riscv_v_widen_constraint_ok): Leverage the above function for\n\tthe register group overlap check.\n\t(riscv_v_widen_non_overlap_constraint_ok): New function to tell\n\tif the register doesn\u0027t overlap the reference register group.\n\t* config/riscv/vector.md: Take the Wn3 constraint for the\n\toperand 4 of the widening integer reduction.\n\nSigned-off-by: Pan Li \u003cpan2.li@intel.com\u003e\n",
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