)]}'
{
  "commit": "6da0b1468bfc4fbf4e8029b9dd634c31cb8261d8",
  "tree": "bc018ff965ab1ac13be89653e3d0eb10a81502bc",
  "parents": [
    "1f54efacc155831aebc13f17f036adec2b56e2ec"
  ],
  "author": {
    "name": "Michiel Derhaeg",
    "email": "michiel.derhaeg@globalfoundries.com",
    "time": "Thu Sep 17 11:38:06 2026 +0300"
  },
  "committer": {
    "name": "Claudiu Zissulescu",
    "email": "claziss@gmail.com",
    "time": "Thu Sep 17 11:38:46 2026 +0300"
  },
  "message": "arc: Don\u0027t advertise optab for unsupported vector modes [PR126243]\n\n\u003cvoptab\u003ev2si3 advertised V2SImode optabs (mul/div/smin/smax) whenever the\nscalar op existed, but V2SImode is only a supported vector mode under\nTARGET_PLUS_QMACW.\n\nSince r15-5493-g485ab50c204ddb (\"Add helpers to test whether an optab\ncan be implemented\") the middle-end keeps the operation vectorized on\nsuch cores.  The operands degrade to DImode and it is expanded as a\ndouble-word scalar op: mul and div silently compute on the packed pair,\nmin and max ICE in expand_expr_real_2 for lack of a DImode expansion.\n\nRequire TARGET_PLUS_QMACW so the optab matches\narc_vector_mode_supported_p.\n\nNo tests added because this is already covered by existing tests.\n\n\tPR target/126243\n\ngcc/ChangeLog:\n\n\t* config/arc/simdext.md (\u003cvoptab\u003ev2si3): Require TARGET_PLUS_QMACW.\n\nSigned-off-by: Michiel Derhaeg \u003cmichiel.derhaeg@globalfoundries.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "15996a1d971299f5346b549a535babd89ffebab0",
      "old_mode": 33188,
      "old_path": "gcc/config/arc/simdext.md",
      "new_id": "4f9bed795ab5273d77fdba62a6b1687452ceddec",
      "new_mode": 33188,
      "new_path": "gcc/config/arc/simdext.md"
    }
  ]
}