)]}'
{
  "commit": "6df026ea07b0cf261bd82a786e867e0bfe70d63c",
  "tree": "2e5f5e087afec217da8b2f7ce57c5afb70d63fec",
  "parents": [
    "ceff533bb4f3c9a49fe30e53caef015961b56d5a"
  ],
  "author": {
    "name": "Bohan Lei",
    "email": "garthlei@linux.alibaba.com",
    "time": "Thu Jul 23 09:36:30 2026 +0800"
  },
  "committer": {
    "name": "Bohan Lei",
    "email": "garthlei@linux.alibaba.com",
    "time": "Thu Jul 30 18:10:28 2026 +0800"
  },
  "message": "RISC-V: Add intrinsic support for Zvabd\n\nThis commit adds intrinsic support for Zvabd.  The original vwabad\nmachine description pattern would cause an ICE when emitting the\nintrinsic because operand 0 and operand 2 are different pseudos,\nand operand 2 has a constraint of \"0\", while operand 0 is marked as\nread-write \"+\".  The vwmacc-like pattern is now used to support correct\nintrinsic generation and to better reflect the semantics.  Pan Li\u0027s new\noverlap constraint is used according to Robin\u0027s review comments of v2.\n\ngcc/ChangeLog:\n\n\t* config/riscv/autovec-opt.md: Match the new vwmacc-like pattern.\n\t* config/riscv/genrvv-type-indexer.cc: Support\n\tDOUBLE_TRUNC_SIGNED type for v[u]int types.\n\t* config/riscv/riscv-vector-builtins-bases.cc (class vabd): New\n\tclass.\n\t(class vabs): Ditto.\n\t(class vabda): Ditto.\n\t(BASE): Define.\n\t* config/riscv/riscv-vector-builtins-bases.h: Ditto.\n\t* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):\n\tDitto.\n\t(vabs): Ditto.\n\t(vabd): Ditto.\n\t(vabdu): Ditto.\n\t(vwabda): Ditto.\n\t(vwabdau): Ditto.\n\t* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_QU_HU_OPS):\n\tDefine.\n\t(DEF_RVV_HU_SU_OPS): Ditto.\n\t* config/riscv/riscv-vector-builtins.cc (qu_hu_ops): Ditto.\n\t(hu_su_ops): Ditto.\n\t(ss_args): Ditto.\n\t(wwss_args): Ditto.\n\t(qu_hu_vss_ops): Ditto\n\t(qu_hu_vvv_ops): Ditto\n\t(hu_su_wwss_ops): Ditto\n\t(hu_su_wwvv_ops): Ditto\n\t(u_s_ops): Ditto\n\t(get_builtin_partition): Add Zvabd case.\n\t* config/riscv/riscv-vector-builtins.h (enum required_ext):\n\tDitto.\n\t(enum rvv_builtin_partition): Ditto.\n\t(required_ext_to_isa_name): Ditto.\n\t(required_extensions_specified): Ditto.\n\t* config/riscv/riscv_vector.h (__riscv_intrinsic_zvabd): Define.\n\t* config/riscv/vector.md: Rewrite pred_widen_abd_plus as\n\tvwmacc-like form.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/base/intrinsic-detection.c: Add Zvabd.\n\t* gcc.target/riscv/rvv/base/zvabd-intrinsic.c: New test.\n",
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