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/* Subroutines for insn-output.c for Renesas H8/300.
Copyright (C) 1992-2021 Free Software Foundation, Inc.
Contributed by Steve Chamberlain (sac@cygnus.com),
Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "target.h"
#include "rtl.h"
#include "tree.h"
#include "df.h"
#include "memmodel.h"
#include "tm_p.h"
#include "stringpool.h"
#include "attribs.h"
#include "optabs.h"
#include "regs.h"
#include "emit-rtl.h"
#include "recog.h"
#include "diagnostic-core.h"
#include "alias.h"
#include "stor-layout.h"
#include "varasm.h"
#include "calls.h"
#include "conditions.h"
#include "output.h"
#include "insn-attr.h"
#include "flags.h"
#include "explow.h"
#include "expr.h"
#include "tm-constrs.h"
#include "builtins.h"
/* This file should be included last. */
#include "target-def.h"
/* Classifies a h8300_src_operand or h8300_dst_operand.
H8OP_IMMEDIATE
A constant operand of some sort.
H8OP_REGISTER
An ordinary register.
H8OP_MEM_ABSOLUTE
A memory reference with a constant address.
H8OP_MEM_BASE
A memory reference with a register as its address.
H8OP_MEM_COMPLEX
Some other kind of memory reference. */
enum h8300_operand_class
{
H8OP_IMMEDIATE,
H8OP_REGISTER,
H8OP_MEM_ABSOLUTE,
H8OP_MEM_BASE,
H8OP_MEM_COMPLEX,
NUM_H8OPS
};
/* For a general two-operand instruction, element [X][Y] gives
the length of the opcode fields when the first operand has class
(X + 1) and the second has class Y. */
typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
/* Forward declarations. */
static const char *byte_reg (rtx, int);
static int h8300_interrupt_function_p (tree);
static int h8300_saveall_function_p (tree);
static int h8300_monitor_function_p (tree);
static int h8300_os_task_function_p (tree);
static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT);
static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
static unsigned int compute_saved_regs (void);
static const char *cond_string (enum rtx_code);
static unsigned int h8300_asm_insn_count (const char *);
static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
static void h8300_print_operand_address (FILE *, machine_mode, rtx);
static void h8300_print_operand (FILE *, rtx, int);
static bool h8300_print_operand_punct_valid_p (unsigned char code);
static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t);
static int h8300_and_costs (rtx);
static int h8300_shift_costs (rtx);
static void h8300_push_pop (int, int, bool, bool);
static int h8300_stack_offset_p (rtx, int);
static int h8300_ldm_stm_regno (rtx, int, int, int);
static void h8300_reorg (void);
static unsigned int h8300_constant_length (rtx);
static unsigned int h8300_displacement_length (rtx, int);
static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
static unsigned int h8300_unary_length (rtx);
static unsigned int h8300_short_immediate_length (rtx);
static unsigned int h8300_bitfield_length (rtx, rtx);
static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
static bool h8300_short_move_mem_p (rtx, enum rtx_code);
static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
static bool h8300_hard_regno_scratch_ok (unsigned int);
static rtx h8300_get_index (rtx, machine_mode mode, int *);
/* CPU_TYPE, says what cpu we're compiling for. */
int cpu_type;
/* True if a #pragma interrupt has been seen for the current function. */
static int pragma_interrupt;
/* True if a #pragma saveall has been seen for the current function. */
static int pragma_saveall;
static const char *const names_big[] =
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc" };
static const char *const names_extended[] =
{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", "cc" };
static const char *const names_upper_extended[] =
{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7", "cc" };
/* Points to one of the above. */
/* ??? The above could be put in an array indexed by CPU_TYPE. */
const char * const *h8_reg_names;
/* Various operations needed by the following, indexed by CPU_TYPE. */
const char *h8_push_op, *h8_pop_op, *h8_mov_op;
/* Value of MOVE_RATIO. */
int h8300_move_ratio;
/* See below where shifts are handled for explanation of this enum. */
enum shift_alg
{
SHIFT_INLINE,
SHIFT_ROT_AND,
SHIFT_SPECIAL,
SHIFT_LOOP
};
/* Symbols of the various shifts which can be used as indices. */
enum shift_type
{
SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
};
/* Macros to keep the shift algorithm tables small. */
#define INL SHIFT_INLINE
#define ROT SHIFT_ROT_AND
#define LOP SHIFT_LOOP
#define SPC SHIFT_SPECIAL
/* The shift algorithms for each machine, mode, shift type, and shift
count are defined below. The three tables below correspond to
QImode, HImode, and SImode, respectively. Each table is organized
by, in the order of indices, machine, shift type, and shift count. */
static enum shift_alg shift_alg_qi[2][3][8] = {
{
/* TARGET_H8300H */
/* 0 1 2 3 4 5 6 7 */
{ INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
{ INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
{ INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
},
{
/* TARGET_H8300S */
/* 0 1 2 3 4 5 6 7 */
{ INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
{ INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
{ INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
}
};
static enum shift_alg shift_alg_hi[2][3][16] = {
{
/* TARGET_H8300H */
/* 0 1 2 3 4 5 6 7 */
/* 8 9 10 11 12 13 14 15 */
{ INL, INL, INL, INL, INL, INL, INL, SPC,
SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
{ INL, INL, INL, INL, INL, INL, INL, SPC,
SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
{ INL, INL, INL, INL, INL, INL, INL, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
},
{
/* TARGET_H8300S */
/* 0 1 2 3 4 5 6 7 */
/* 8 9 10 11 12 13 14 15 */
{ INL, INL, INL, INL, INL, INL, INL, INL,
SPC, SPC, SPC, SPC, ROT, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
{ INL, INL, INL, INL, INL, INL, INL, INL,
SPC, SPC, SPC, SPC, ROT, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
{ INL, INL, INL, INL, INL, INL, INL, INL,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
}
};
static enum shift_alg shift_alg_si[2][3][32] = {
{
/* TARGET_H8300H */
/* 0 1 2 3 4 5 6 7 */
/* 8 9 10 11 12 13 14 15 */
/* 16 17 18 19 20 21 22 23 */
/* 24 25 26 27 28 29 30 31 */
{ INL, INL, INL, INL, INL, INL, INL, LOP,
SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
{ INL, INL, INL, INL, INL, INL, INL, LOP,
SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
{ INL, INL, INL, INL, INL, INL, INL, LOP,
SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
},
{
/* TARGET_H8300S */
/* 0 1 2 3 4 5 6 7 */
/* 8 9 10 11 12 13 14 15 */
/* 16 17 18 19 20 21 22 23 */
/* 24 25 26 27 28 29 30 31 */
{ INL, INL, INL, INL, INL, INL, INL, INL,
INL, INL, INL, INL, INL, INL, INL, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
{ INL, INL, INL, INL, INL, INL, INL, INL,
INL, INL, INL, INL, INL, INL, INL, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
{ INL, INL, INL, INL, INL, INL, INL, INL,
INL, INL, INL, INL, INL, INL, INL, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC,
SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
}
};
#undef INL
#undef ROT
#undef LOP
#undef SPC
enum h8_cpu
{
H8_300H,
H8_S
};
/* Initialize various cpu specific globals at start up. */
static void
h8300_option_override (void)
{
static const char *const h8_push_ops[2] = { "push" , "push.l" };
static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
/* For this we treat the H8/300H and H8S the same. */
cpu_type = (int) CPU_H8300H;
h8_reg_names = names_extended;
h8_push_op = h8_push_ops[cpu_type];
h8_pop_op = h8_pop_ops[cpu_type];
h8_mov_op = h8_mov_ops[cpu_type];
/* If we're compiling for the H8/S, then turn off H8/300H. */
if (TARGET_H8300S)
target_flags &= ~MASK_H8300H;
if (!TARGET_H8300S && TARGET_MAC)
{
error ("%<-ms2600%> is used without %<-ms%>");
target_flags |= MASK_H8300S_1;
}
if (! TARGET_H8300S && TARGET_EXR)
{
error ("%<-mexr%> is used without %<-ms%>");
target_flags |= MASK_H8300S_1;
}
if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
{
error ("%<-mexr%> is used without %<-ms%> or %<-msx%>");
target_flags |= MASK_H8300S_1;
}
if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
{
warning (OPT_mno_exr, "%<-mno-exr%> is valid only with %<-ms%> or "
"%<-msx%> - option ignored");
}
#ifdef H8300_LINUX
if ((TARGET_NORMAL_MODE))
{
error ("%<-mn%> is not supported for linux targets");
target_flags ^= MASK_NORMAL_MODE;
}
#endif
/* Some of the shifts are optimized for speed by default.
See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
If optimizing for size, change shift_alg for those shift to
SHIFT_LOOP. */
if (optimize_size)
{
/* H8/300H */
shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFT][20] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFT][21] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFT][22] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFT][23] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFT][25] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFT][26] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFT][27] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_LSHIFTRT][20] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_LSHIFTRT][21] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_LSHIFTRT][22] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_LSHIFTRT][23] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_LSHIFTRT][25] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_LSHIFTRT][26] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_LSHIFTRT][27] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][20] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][21] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][22] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][23] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][25] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][26] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][27] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][28] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][29] = SHIFT_LOOP;
shift_alg_si[H8_300H][SHIFT_ASHIFTRT][30] = SHIFT_LOOP;
/* H8S */
shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFT][11] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFT][12] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFT][13] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFT][14] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFT][22] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFT][23] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFT][26] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFT][27] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_LSHIFTRT][11] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_LSHIFTRT][12] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_LSHIFTRT][22] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_LSHIFTRT][23] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_LSHIFTRT][26] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_LSHIFTRT][27] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][11] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][12] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][22] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][23] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][26] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][27] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][28] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][29] = SHIFT_LOOP;
shift_alg_si[H8_S][SHIFT_ASHIFTRT][30] = SHIFT_LOOP;
}
/* Work out a value for MOVE_RATIO. */
if (!TARGET_H8300SX)
{
/* Memory-memory moves are quite expensive without the
h8sx instructions. */
h8300_move_ratio = 3;
}
else if (flag_omit_frame_pointer)
{
/* movmd sequences are fairly cheap when er6 isn't fixed. They can
sometimes be as short as two individual memory-to-memory moves,
but since they use all the call-saved registers, it seems better
to allow up to three moves here. */
h8300_move_ratio = 4;
}
else if (optimize_size)
{
/* In this case we don't use movmd sequences since they tend
to be longer than calls to memcpy(). Memory-to-memory
moves are cheaper than for !TARGET_H8300SX, so it makes
sense to have a slightly higher threshold. */
h8300_move_ratio = 4;
}
else
{
/* We use movmd sequences for some moves since it can be quicker
than calling memcpy(). The sequences will need to save and
restore er6 though, so bump up the cost. */
h8300_move_ratio = 6;
}
/* This target defaults to strict volatile bitfields. */
if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
flag_strict_volatile_bitfields = 1;
}
/* Return the byte register name for a register rtx X. B should be 0
if you want a lower byte register. B should be 1 if you want an
upper byte register. */
static const char *
byte_reg (rtx x, int b)
{
static const char *const names_small[] = {
"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
"r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
};
gcc_assert (REG_P (x));
return names_small[REGNO (x) * 2 + b];
}
/* REGNO must be saved/restored across calls if this macro is true. */
#define WORD_REG_USED(regno) \
(regno < SP_REG \
/* No need to save registers if this function will not return. */ \
&& ! TREE_THIS_VOLATILE (current_function_decl) \
&& (h8300_saveall_function_p (current_function_decl) \
/* Save any call saved register that was used. */ \
|| (df_regs_ever_live_p (regno) \
&& !call_used_or_fixed_reg_p (regno)) \
/* Save the frame pointer if it was used. */ \
|| (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
/* Save any register used in an interrupt handler. */ \
|| (h8300_current_function_interrupt_function_p () \
&& df_regs_ever_live_p (regno)) \
/* Save call clobbered registers in non-leaf interrupt \
handlers. */ \
|| (h8300_current_function_interrupt_function_p () \
&& call_used_or_fixed_reg_p (regno) \
&& !crtl->is_leaf)))
/* We use this to wrap all emitted insns in the prologue. */
static rtx_insn *
F (rtx_insn *x, bool set_it)
{
if (set_it)
RTX_FRAME_RELATED_P (x) = 1;
return x;
}
/* Mark all the subexpressions of the PARALLEL rtx PAR as
frame-related. Return PAR.
dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
PARALLEL rtx other than the first if they do not have the
FRAME_RELATED flag set on them. */
static rtx
Fpa (rtx par)
{
int len = XVECLEN (par, 0);
int i;
for (i = 0; i < len; i++)
RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1;
return par;
}
/* Output assembly language to FILE for the operation OP with operand size
SIZE to adjust the stack pointer. */
static void
h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size)
{
/* If the frame size is 0, we don't have anything to do. */
if (size == 0)
return;
/* The stack adjustment made here is further optimized by the
splitter. In case of H8/300, the splitter always splits the
addition emitted here to make the adjustment interrupt-safe.
FIXME: We don't always tag those, because we don't know what
the splitter will do. */
if (Pmode == HImode)
{
rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (sign * size)));
if (size < 4)
F (x, 0);
}
else
F (emit_insn (gen_addsi3 (stack_pointer_rtx,
stack_pointer_rtx, GEN_INT (sign * size))), 0);
}
/* Round up frame size SIZE. */
static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT size)
{
return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
& -STACK_BOUNDARY / BITS_PER_UNIT);
}
/* Compute which registers to push/pop.
Return a bit vector of registers. */
static unsigned int
compute_saved_regs (void)
{
unsigned int saved_regs = 0;
int regno;
/* Construct a bit vector of registers to be pushed/popped. */
for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
{
if (WORD_REG_USED (regno))
saved_regs |= 1 << regno;
}
/* Don't push/pop the frame pointer as it is treated separately. */
if (frame_pointer_needed)
saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
return saved_regs;
}
/* Emit an insn to push register RN. */
static rtx
push (int rn)
{
rtx reg = gen_rtx_REG (word_mode, rn);
rtx x;
if (!TARGET_NORMAL_MODE)
x = gen_push_h8300hs_advanced (reg);
else
x = gen_push_h8300hs_normal (reg);
x = F (emit_insn (x), 0);
add_reg_note (x, REG_INC, stack_pointer_rtx);
return x;
}
/* Emit an insn to pop register RN. */
static rtx
pop (int rn)
{
rtx reg = gen_rtx_REG (word_mode, rn);
rtx x;
if (!TARGET_NORMAL_MODE)
x = gen_pop_h8300hs_advanced (reg);
else
x = gen_pop_h8300hs_normal (reg);
x = emit_insn (x);
add_reg_note (x, REG_INC, stack_pointer_rtx);
return x;
}
/* Emit an instruction to push or pop NREGS consecutive registers
starting at register REGNO. POP_P selects a pop rather than a
push and RETURN_P is true if the instruction should return.
It must be possible to do the requested operation in a single
instruction. If NREGS == 1 && !RETURN_P, use a normal push
or pop insn. Otherwise emit a parallel of the form:
(parallel
[(return) ;; if RETURN_P
(save or restore REGNO)
(save or restore REGNO + 1)
...
(save or restore REGNO + NREGS - 1)
(set sp (plus sp (const_int adjust)))] */
static void
h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
{
int i, j;
rtvec vec;
rtx sp, offset, x;
/* See whether we can use a simple push or pop. */
if (!return_p && nregs == 1)
{
if (pop_p)
pop (regno);
else
push (regno);
return;
}
/* We need one element for the return insn, if present, one for each
register, and one for stack adjustment. */
vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
sp = stack_pointer_rtx;
i = 0;
/* Add the return instruction. */
if (return_p)
{
RTVEC_ELT (vec, i) = ret_rtx;
i++;
}
/* Add the register moves. */
for (j = 0; j < nregs; j++)
{
rtx lhs, rhs;
if (pop_p)
{
/* Register REGNO + NREGS - 1 is popped first. Before the
stack adjustment, its slot is at address @sp. */
lhs = gen_rtx_REG (SImode, regno + j);
rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
(nregs - j - 1) * 4));
}
else
{
/* Register REGNO is pushed first and will be stored at @(-4,sp). */
lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
rhs = gen_rtx_REG (SImode, regno + j);
}
RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs);
}
/* Add the stack adjustment. */
offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset));
x = gen_rtx_PARALLEL (VOIDmode, vec);
if (!pop_p)
x = Fpa (x);
if (return_p)
emit_jump_insn (x);
else
emit_insn (x);
}
/* Return true if X has the value sp + OFFSET. */
static int
h8300_stack_offset_p (rtx x, int offset)
{
if (offset == 0)
return x == stack_pointer_rtx;
return (GET_CODE (x) == PLUS
&& XEXP (x, 0) == stack_pointer_rtx
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& INTVAL (XEXP (x, 1)) == offset);
}
/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
something that may be an ldm or stm instruction. If it fits
the required template, return the register it loads or stores,
otherwise return -1.
LOAD_P is true if X should be a load, false if it should be a store.
NREGS is the number of registers that the whole instruction is expected
to load or store. INDEX is the index of the register that X should
load or store, relative to the lowest-numbered register. */
static int
h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
{
int regindex, memindex, offset;
if (load_p)
regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
else
memindex = 0, regindex = 1, offset = (index + 1) * -4;
if (GET_CODE (x) == SET
&& GET_CODE (XEXP (x, regindex)) == REG
&& GET_CODE (XEXP (x, memindex)) == MEM
&& h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
return REGNO (XEXP (x, regindex));
return -1;
}
/* Return true if the elements of VEC starting at FIRST describe an
ldm or stm instruction (LOAD_P says which). */
int
h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
{
rtx last;
int nregs, i, regno, adjust;
/* There must be a stack adjustment, a register move, and at least one
other operation (a return or another register move). */
if (GET_NUM_ELEM (vec) < 3)
return false;
/* Get the range of registers to be pushed or popped. */
nregs = GET_NUM_ELEM (vec) - first - 1;
regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
/* Check that the call to h8300_ldm_stm_regno succeeded and
that we're only dealing with GPRs. */
if (regno < 0 || regno + nregs > 8)
return false;
/* 2-register h8s instructions must start with an even-numbered register.
3- and 4-register instructions must start with er0 or er4. */
if (!TARGET_H8300SX)
{
if ((regno & 1) != 0)
return false;
if (nregs > 2 && (regno & 3) != 0)
return false;
}
/* Check the other loads or stores. */
for (i = 1; i < nregs; i++)
if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
!= regno + i)
return false;
/* Check the stack adjustment. */
last = RTVEC_ELT (vec, first + nregs);
adjust = (load_p ? nregs : -nregs) * 4;
return (GET_CODE (last) == SET
&& SET_DEST (last) == stack_pointer_rtx
&& h8300_stack_offset_p (SET_SRC (last), adjust));
}
/* This is what the stack looks like after the prolog of
a function with a frame has been set up:
<args>
PC
FP <- fp
<locals>
<saved registers> <- sp
This is what the stack looks like after the prolog of
a function which doesn't have a frame:
<args>
PC
<locals>
<saved registers> <- sp
*/
/* Generate RTL code for the function prologue. */
void
h8300_expand_prologue (void)
{
int regno;
int saved_regs;
int n_regs;
/* If the current function has the OS_Task attribute set, then
we have a naked prologue. */
if (h8300_os_task_function_p (current_function_decl))
return;
if (h8300_monitor_function_p (current_function_decl))
/* The monitor function act as normal functions, which means it
can accept parameters and return values. In addition to this,
interrupts are masked in prologue and return with "rte" in epilogue. */
emit_insn (gen_monitor_prologue ());
if (frame_pointer_needed)
{
/* Push fp. */
push (HARD_FRAME_POINTER_REGNUM);
F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), 0);
}
/* Push the rest of the registers in ascending order. */
saved_regs = compute_saved_regs ();
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
{
n_regs = 1;
if (saved_regs & (1 << regno))
{
if (TARGET_H8300S)
{
/* See how many registers we can push at the same time. */
if ((TARGET_H8300SX || (regno & 3) == 0)
&& ((saved_regs >> regno) & 0x0f) == 0x0f)
n_regs = 4;
else if ((TARGET_H8300SX || (regno & 3) == 0)
&& ((saved_regs >> regno) & 0x07) == 0x07)
n_regs = 3;
else if ((TARGET_H8300SX || (regno & 1) == 0)
&& ((saved_regs >> regno) & 0x03) == 0x03)
n_regs = 2;
}
h8300_push_pop (regno, n_regs, false, false);
}
}
/* Leave room for locals. */
h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
if (flag_stack_usage_info)
current_function_static_stack_size
= round_frame_size (get_frame_size ())
+ (__builtin_popcount (saved_regs) * UNITS_PER_WORD)
+ (frame_pointer_needed ? UNITS_PER_WORD : 0);
}
/* Return nonzero if we can use "rts" for the function currently being
compiled. */
int
h8300_can_use_return_insn_p (void)
{
return (reload_completed
&& !frame_pointer_needed
&& get_frame_size () == 0
&& compute_saved_regs () == 0);
}
/* Generate RTL code for the function epilogue. */
void
h8300_expand_epilogue (bool sibcall_p)
{
int regno;
int saved_regs;
int n_regs;
HOST_WIDE_INT frame_size;
bool returned_p;
if (h8300_os_task_function_p (current_function_decl))
/* OS_Task epilogues are nearly naked -- they just have an
rts instruction. */
return;
frame_size = round_frame_size (get_frame_size ());
returned_p = false;
/* Deallocate locals. */
h8300_emit_stack_adjustment (1, frame_size);
/* Pop the saved registers in descending order. */
saved_regs = compute_saved_regs ();
for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
{
n_regs = 1;
if (saved_regs & (1 << regno))
{
if (TARGET_H8300S)
{
/* See how many registers we can pop at the same time. */
if ((TARGET_H8300SX || (regno & 3) == 3)
&& ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
n_regs = 4;
else if ((TARGET_H8300SX || (regno & 3) == 2)
&& ((saved_regs << 2 >> regno) & 0x07) == 0x07)
n_regs = 3;
else if ((TARGET_H8300SX || (regno & 1) == 1)
&& ((saved_regs << 1 >> regno) & 0x03) == 0x03)
n_regs = 2;
}
/* See if this pop would be the last insn before the return.
If so, use rte/l or rts/l instead of pop or ldm.l. */
if (TARGET_H8300SX
&& !sibcall_p
&& !frame_pointer_needed
&& frame_size == 0
&& (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
returned_p = true;
h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
}
}
/* Pop frame pointer if we had one. */
if (frame_pointer_needed)
{
if (TARGET_H8300SX && !sibcall_p)
returned_p = true;
h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
}
if (!returned_p && !sibcall_p)
emit_jump_insn (ret_rtx);
}
/* Return nonzero if the current function is an interrupt
function. */
int
h8300_current_function_interrupt_function_p (void)
{
return (h8300_interrupt_function_p (current_function_decl));
}
int
h8300_current_function_monitor_function_p ()
{
return (h8300_monitor_function_p (current_function_decl));
}
/* Output assembly code for the start of the file. */
static void
h8300_file_start (void)
{
default_file_start ();
if (TARGET_H8300SX)
fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
else if (TARGET_H8300S)
fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
else if (TARGET_H8300H)
fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
}
/* Output assembly language code for the end of file. */
static void
h8300_file_end (void)
{
fputs ("\t.end\n", asm_out_file);
}
/* Split an add of a small constant into two adds/subs insns.
If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
instead of adds/subs. */
void
split_adds_subs (machine_mode mode, rtx *operands)
{
HOST_WIDE_INT val = INTVAL (operands[1]);
rtx reg = operands[0];
HOST_WIDE_INT sign = 1;
HOST_WIDE_INT amount;
rtx (*gen_add) (rtx, rtx, rtx);
/* Force VAL to be positive so that we do not have to consider the
sign. */
if (val < 0)
{
val = -val;
sign = -1;
}
switch (mode)
{
case E_HImode:
gen_add = gen_addhi3;
break;
case E_SImode:
gen_add = gen_addsi3;
break;
default:
gcc_unreachable ();
}
/* Try different amounts in descending order. */
for (amount = 4; amount > 0; amount /= 2)
{
for (; val >= amount; val -= amount)
emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
}
return;
}
/* Handle machine specific pragmas for compatibility with existing
compilers for the H8/300.
pragma saveall generates prologue/epilogue code which saves and
restores all the registers on function entry.
pragma interrupt saves and restores all registers, and exits with
an rte instruction rather than an rts. A pointer to a function
with this attribute may be safely used in an interrupt vector. */
void
h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
{
pragma_interrupt = 1;
}
void
h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
{
pragma_saveall = 1;
}
/* If the next function argument ARG is to be passed in a register, return
a reg RTX for the hard register in which to pass the argument. CUM
represents the state after the last argument. If the argument is to
be pushed, NULL_RTX is returned.
On the H8/300 all normal args are pushed, unless -mquickcall in which
case the first 3 arguments are passed in registers. */
static rtx
h8300_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
static const char *const hand_list[] = {
"__main",
"__cmpsi2",
"__divhi3",
"__modhi3",
"__udivhi3",
"__umodhi3",
"__divsi3",
"__modsi3",
"__udivsi3",
"__umodsi3",
"__mulhi3",
"__mulsi3",
"__reg_memcpy",
"__reg_memset",
"__ucmpsi2",
0,
};
rtx result = NULL_RTX;
const char *fname;
int regpass = 0;
/* Never pass unnamed arguments in registers. */
if (!arg.named)
return NULL_RTX;
/* Pass 3 regs worth of data in regs when user asked on the command line. */
if (TARGET_QUICKCALL)
regpass = 3;
/* If calling hand written assembler, use 4 regs of args. */
if (cum->libcall)
{
const char * const *p;
fname = XSTR (cum->libcall, 0);
/* See if this libcall is one of the hand coded ones. */
for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
;
if (*p)
regpass = 4;
}
if (regpass)
{
int size = arg.promoted_size_in_bytes ();
if (size + cum->nbytes <= regpass * UNITS_PER_WORD
&& cum->nbytes / UNITS_PER_WORD <= 3)
result = gen_rtx_REG (arg.mode, cum->nbytes / UNITS_PER_WORD);
}
return result;
}
/* Update the data in CUM to advance over argument ARG. */
static void
h8300_function_arg_advance (cumulative_args_t cum_v,
const function_arg_info &arg)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
cum->nbytes += ((arg.promoted_size_in_bytes () + UNITS_PER_WORD - 1)
& -UNITS_PER_WORD);
}
/* Implements TARGET_REGISTER_MOVE_COST.
Any SI register-to-register move may need to be reloaded,
so inmplement h8300_register_move_cost to return > 2 so that reload never
shortcuts. */
static int
h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
reg_class_t from, reg_class_t to)
{
if (from == MAC_REGS || to == MAC_REG)
return 6;
else
return 3;
}
/* Compute the cost of an and insn. */
static int
h8300_and_costs (rtx x)
{
rtx operands[4];
if (GET_MODE (x) == QImode)
return 1;
if (GET_MODE (x) != HImode
&& GET_MODE (x) != SImode)
return 100;
operands[0] = NULL;
operands[1] = XEXP (x, 0);
operands[2] = XEXP (x, 1);
operands[3] = x;
return compute_logical_op_length (GET_MODE (x), AND, operands, NULL) / 2;
}
/* Compute the cost of a shift insn. */
static int
h8300_shift_costs (rtx x)
{
rtx operands[3];
if (GET_MODE (x) != QImode
&& GET_MODE (x) != HImode
&& GET_MODE (x) != SImode)
return 100;
operands[0] = gen_rtx_REG (GET_MODE (x), 0);
operands[1] = NULL;
operands[2] = XEXP (x, 1);
return compute_a_shift_length (operands, GET_CODE (x)) / 2;
}
/* Worker function for TARGET_RTX_COSTS. */
static bool
h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
int opno ATTRIBUTE_UNUSED, int *total, bool speed)
{
int code = GET_CODE (x);
if (TARGET_H8300SX && outer_code == MEM)
{
/* Estimate the number of execution states needed to calculate
the address. */
if (register_operand (x, VOIDmode)
|| GET_CODE (x) == POST_INC
|| GET_CODE (x) == POST_DEC
|| CONSTANT_P (x))
*total = 0;
else
*total = COSTS_N_INSNS (1);
return true;
}
switch (code)
{
case CONST_INT:
{
HOST_WIDE_INT n = INTVAL (x);
if (TARGET_H8300SX)
{
/* Constant operands need the same number of processor
states as register operands. Although we could try to
use a size-based cost for !speed, the lack of
of a mode makes the results very unpredictable. */
*total = 0;
return true;
}
if (n >= -4 && n <= 4)
{
switch ((int) n)
{
case 0:
*total = 0;
return true;
case 1:
case 2:
case -1:
case -2:
*total = 0 + (outer_code == SET);
return true;
case 4:
case -4:
*total = 0 + (outer_code == SET);
return true;
}
}
*total = 1;
return true;
}
case CONST:
case LABEL_REF:
case SYMBOL_REF:
if (TARGET_H8300SX)
{
/* See comment for CONST_INT. */
*total = 0;
return true;
}
*total = 3;
return true;
case CONST_DOUBLE:
*total = 20;
return true;
case COMPARE:
case NE:
case EQ:
case GE:
case GT:
case LE:
case LT:
case GEU:
case GTU:
case LEU:
case LTU:
if (XEXP (x, 1) == const0_rtx)
*total = 0;
return false;
case AND:
if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
|| !h8300_src_operand (XEXP (x, 1), VOIDmode))
return false;
*total = COSTS_N_INSNS (h8300_and_costs (x));
return true;
/* We say that MOD and DIV are so expensive because otherwise we'll
generate some really horrible code for division of a power of two. */
case MOD:
case DIV:
case UMOD:
case UDIV:
if (TARGET_H8300SX)
switch (GET_MODE (x))
{
case E_QImode:
case E_HImode:
*total = COSTS_N_INSNS (!speed ? 4 : 10);
return false;
case E_SImode:
*total = COSTS_N_INSNS (!speed ? 4 : 18);
return false;
default:
break;
}
*total = COSTS_N_INSNS (12);
return true;
case MULT:
if (TARGET_H8300SX)
switch (GET_MODE (x))
{
case E_QImode:
case E_HImode:
*total = COSTS_N_INSNS (2);
return false;
case E_SImode:
*total = COSTS_N_INSNS (5);
return false;
default:
break;
}
*total = COSTS_N_INSNS (4);
return true;
case ASHIFT:
case ASHIFTRT:
case LSHIFTRT:
if (h8sx_binary_shift_operator (x, VOIDmode))
{
*total = COSTS_N_INSNS (2);
return false;
}
else if (h8sx_unary_shift_operator (x, VOIDmode))
{
*total = COSTS_N_INSNS (1);
return false;
}
*total = COSTS_N_INSNS (h8300_shift_costs (x));
return true;
case ROTATE:
case ROTATERT:
if (GET_MODE (x) == HImode)
*total = 2;
else
*total = 8;
return true;
default:
*total = COSTS_N_INSNS (1);
return false;
}
}
/* Documentation for the machine specific operand escapes:
'E' like s but negative.
'F' like t but negative.
'G' constant just the negative
'R' print operand as a byte:8 address if appropriate, else fall back to
'X' handling.
'S' print operand as a long word
'T' print operand as a word
'V' find the set bit, and print its number.
'W' find the clear bit, and print its number.
'X' print operand as a byte
'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
If this operand isn't a register, fall back to 'R' handling.
'Z' print int & 7.
'c' print the opcode corresponding to rtl
'e' first word of 32-bit value - if reg, then least reg. if mem
then least. if const then most sig word
'f' second word of 32-bit value - if reg, then biggest reg. if mem
then +2. if const then least sig word
'j' print operand as condition code.
'k' print operand as reverse condition code.
'm' convert an integer operand to a size suffix (.b, .w or .l)
'o' print an integer without a leading '#'
's' print as low byte of 16-bit value
't' print as high byte of 16-bit value
'w' print as low byte of 32-bit value
'x' print as 2nd byte of 32-bit value
'y' print as 3rd byte of 32-bit value
'z' print as msb of 32-bit value
*/
/* Return assembly language string which identifies a comparison type. */
static const char *
cond_string (enum rtx_code code)
{
switch (code)
{
case NE:
return "ne";
case EQ:
return "eq";
case GE:
return "ge";
case GT:
return "gt";
case LE:
return "le";
case LT:
return "lt";
case GEU:
return "hs";
case GTU:
return "hi";
case LEU:
return "ls";
case LTU:
return "lo";
default:
gcc_unreachable ();
}
}
/* Print operand X using operand code CODE to assembly language output file
FILE. */
static void
h8300_print_operand (FILE *file, rtx x, int code)
{
/* This is used for communication between codes V,W,Z and Y. */
static int bitint;
switch (code)
{
case 'C':
if (h8300_constant_length (x) == 2)
fprintf (file, ":16");
else
fprintf (file, ":32");
return;
case 'E':
switch (GET_CODE (x))
{
case REG:
fprintf (file, "%sl", names_big[REGNO (x)]);
break;
case CONST_INT:
fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
break;
default:
gcc_unreachable ();
}
break;
case 'F':
switch (GET_CODE (x))
{
case REG:
fprintf (file, "%sh", names_big[REGNO (x)]);
break;
case CONST_INT:
fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
break;
default:
gcc_unreachable ();
}
break;
case 'G':
gcc_assert (GET_CODE (x) == CONST_INT);
fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
break;
case 'S':
if (GET_CODE (x) == REG)
fprintf (file, "%s", names_extended[REGNO (x)]);
else
goto def;
break;
case 'T':
if (GET_CODE (x) == REG)
fprintf (file, "%s", names_big[REGNO (x)]);
else
goto def;
break;
case 'V':
bitint = (INTVAL (x) & 0xffff);
if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
bitint = exact_log2 (bitint & 0xff);
else
bitint = exact_log2 ((bitint >> 8) & 0xff);
gcc_assert (bitint >= 0);
fprintf (file, "#%d", bitint);
break;
case 'W':
bitint = ((~INTVAL (x)) & 0xffff);
if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
bitint = exact_log2 (bitint & 0xff);
else
bitint = (exact_log2 ((bitint >> 8) & 0xff));
gcc_assert (bitint >= 0);
fprintf (file, "#%d", bitint);
break;
case 'R':
case 'X':
if (GET_CODE (x) == REG)
fprintf (file, "%s", byte_reg (x, 0));
else
goto def;
break;
case 'Y':
gcc_assert (bitint >= 0);
if (GET_CODE (x) == REG)
fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
else
h8300_print_operand (file, x, 'R');
bitint = -1;
break;
case 'Z':
bitint = INTVAL (x);
fprintf (file, "#%d", bitint & 7);
break;
case 'c':
switch (GET_CODE (x))
{
case IOR:
fprintf (file, "or");
break;
case XOR:
fprintf (file, "xor");
break;
case AND:
fprintf (file, "and");
break;
default:
break;
}
break;
case 'e':
switch (GET_CODE (x))
{
case REG:
fprintf (file, "%s", names_upper_extended[REGNO (x)]);
break;
case MEM:
h8300_print_operand (file, x, 0);
break;
case CONST_INT:
fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
break;
case CONST_DOUBLE:
{
long val;
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
fprintf (file, "#%ld", ((val >> 16) & 0xffff));
break;
}
default:
gcc_unreachable ();
break;
}
break;
case 'f':
switch (GET_CODE (x))
{
case REG:
fprintf (file, "%s", names_big[REGNO (x)]);
break;
case MEM:
x = adjust_address (x, HImode, 2);
h8300_print_operand (file, x, 0);
break;
case CONST_INT:
fprintf (file, "#%ld", INTVAL (x) & 0xffff);
break;
case CONST_DOUBLE:
{
long val;
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
fprintf (file, "#%ld", (val & 0xffff));
break;
}
default:
gcc_unreachable ();
}
break;
case 'j':
if (GET_CODE (x) == LT && GET_MODE (XEXP (x, 0)) == E_CCZNmode)
fputs ("mi", file);
else if (GET_CODE (x) == GE && GET_MODE (XEXP (x, 0)) == E_CCZNmode)
fputs ("pl", file);
else
fputs (cond_string (GET_CODE (x)), file);
break;
case 'k':
if (GET_CODE (x) == LT && GET_MODE (XEXP (x, 0)) == E_CCZNmode)
fputs ("pl", file);
else if (GET_CODE (x) == GE && GET_MODE (XEXP (x, 0)) == E_CCZNmode)
fputs ("mi", file);
else
fputs (cond_string (reverse_condition (GET_CODE (x))), file);
break;
case 'm':
gcc_assert (GET_CODE (x) == CONST_INT);
switch (INTVAL (x))
{
case 1:
fputs (".b", file);
break;
case 2:
fputs (".w", file);
break;
case 4:
fputs (".l", file);
break;
default:
gcc_unreachable ();
}
break;
case 'o':
h8300_print_operand_address (file, VOIDmode, x);
break;
case 's':
if (GET_CODE (x) == CONST_INT)
fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
else if (GET_CODE (x) == REG)
fprintf (file, "%s", byte_reg (x, 0));
else
output_operand_lossage ("Expected register or constant integer.");
break;
case 't':
if (GET_CODE (x) == CONST_INT)
fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
else if (GET_CODE (x) == REG)
fprintf (file, "%s", byte_reg (x, 1));
else
output_operand_lossage ("Expected register or constant integer.");
break;
case 'w':
if (GET_CODE (x) == CONST_INT)
fprintf (file, "#%ld", INTVAL (x) & 0xff);
else if (GET_CODE (x) == REG)
fprintf (file, "%s", byte_reg (x, 0));
else
output_operand_lossage ("Expected register or constant integer.");
break;
case 'x':
if (GET_CODE (x) == CONST_INT)
fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
else if (GET_CODE (x) == REG)
fprintf (file, "%s", byte_reg (x, 1));
else
output_operand_lossage ("Expected register or constant integer.");
break;
case 'y':
if (GET_CODE (x) == CONST_INT)
fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
else if (GET_CODE (x) == REG)
fprintf (file, "%s", byte_reg (x, 0));
else
output_operand_lossage ("Expected register or constant integer.");
break;
case 'z':
if (GET_CODE (x) == CONST_INT)
fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
else if (GET_CODE (x) == REG)
fprintf (file, "%s", byte_reg (x, 1));
else
output_operand_lossage ("Expected register or constant integer.");
break;
default:
def:
switch (GET_CODE (x))
{
case REG:
switch (GET_MODE (x))
{
case E_QImode:
#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
fprintf (file, "%s", byte_reg (x, 0));
#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
fprintf (file, "%s", names_big[REGNO (x)]);
#endif
break;
case E_HImode:
fprintf (file, "%s", names_big[REGNO (x)]);
break;
case E_SImode:
case E_SFmode:
fprintf (file, "%s", names_extended[REGNO (x)]);
break;
default:
gcc_unreachable ();
}
break;
case MEM:
{
rtx addr = XEXP (x, 0);
fprintf (file, "@");
output_address (GET_MODE (x), addr);
/* Add a length suffix to constant addresses. Although this
is often unnecessary, it helps to avoid ambiguity in the
syntax of mova. If we wrote an insn like:
mova/w.l @(1,@foo.b),er0
then .b would be considered part of the symbol name.
Adding a length after foo will avoid this. */
if (CONSTANT_P (addr))
switch (code)
{
case 'R':
/* Used for mov.b and bit operations. */
if (h8300_eightbit_constant_address_p (addr))
{
fprintf (file, ":8");
break;
}
/* FALLTHRU */
/* We should not get here if we are processing bit
operations on H8/300 or H8/300H because 'U'
constraint does not allow bit operations on the
tiny area on these machines. */
case 'X':
case 'T':
case 'S':
if (h8300_constant_length (addr) == 2)
fprintf (file, ":16");
else
fprintf (file, ":32");
break;
default:
break;
}
}
break;
case CONST_INT:
case SYMBOL_REF:
case CONST:
case LABEL_REF:
fprintf (file, "#");
h8300_print_operand_address (file, VOIDmode, x);
break;
case CONST_DOUBLE:
{
long val;
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
fprintf (file, "#%ld", val);
break;
}
default:
break;
}
}
}
/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
static bool
h8300_print_operand_punct_valid_p (unsigned char code)
{
return (code == '#');
}
/* Output assembly language output for the address ADDR to FILE. */
static void
h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr)
{
rtx index;
int size;
switch (GET_CODE (addr))
{
case REG:
fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
break;
case PRE_DEC:
fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
break;
case POST_INC:
fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
break;
case PRE_INC:
fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
break;
case POST_DEC:
fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
break;
case PLUS:
fprintf (file, "(");
index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
if (GET_CODE (index) == REG)
{
/* reg,foo */
h8300_print_operand_address (file, mode, XEXP (addr, 1));
fprintf (file, ",");
switch (size)
{
case 0:
h8300_print_operand_address (file, mode, index);
break;
case 1:
h8300_print_operand (file, index, 'X');
fputs (".b", file);
break;
case 2:
h8300_print_operand (file, index, 'T');
fputs (".w", file);
break;
case 4:
h8300_print_operand (file, index, 'S');
fputs (".l", file);
break;
}
/* h8300_print_operand_address (file, XEXP (addr, 0)); */
}
else
{
/* foo+k */
h8300_print_operand_address (file, mode, XEXP (addr, 0));
fprintf (file, "+");
h8300_print_operand_address (file, mode, XEXP (addr, 1));
}
fprintf (file, ")");
break;
case CONST_INT:
{
int n = INTVAL (addr);
fprintf (file, "%d", n);
break;
}
default:
output_addr_const (file, addr);
break;
}
}
/* Output all insn addresses and their sizes into the assembly language
output file. This is helpful for debugging whether the length attributes
in the md file are correct. This is not meant to be a user selectable
option. */
void
final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
int num_operands ATTRIBUTE_UNUSED)
{
/* This holds the last insn address. */
static int last_insn_address = 0;
const int uid = INSN_UID (insn);
if (TARGET_ADDRESSES)
{
fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
INSN_ADDRESSES (uid) - last_insn_address);
last_insn_address = INSN_ADDRESSES (uid);
}
}
/* Prepare for an SI sized move. */
int
h8300_expand_movsi (rtx operands[])
{
rtx src = operands[1];
rtx dst = operands[0];
if (!reload_in_progress && !reload_completed)
{
if (!register_operand (dst, GET_MODE (dst)))
{
rtx tmp = gen_reg_rtx (GET_MODE (dst));
emit_move_insn (tmp, src);
operands[1] = tmp;
}
}
return 0;
}
/* Given FROM and TO register numbers, say whether this elimination is allowed.
Frame pointer elimination is automatically handled.
For the h8300, if frame pointer elimination is being done, we would like to
convert ap and rp into sp, not fp.
All other eliminations are valid. */
static bool
h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
{
return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
}
/* Conditionally modify register usage based on target flags. */
static void
h8300_conditional_register_usage (void)
{
if (!TARGET_MAC)
fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
}
/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
Define the offset between two registers, one to be eliminated, and
the other its replacement, at the start of a routine. */
int
h8300_initial_elimination_offset (int from, int to)
{
/* The number of bytes that the return address takes on the stack. */
int pc_size = POINTER_SIZE / BITS_PER_UNIT;
/* The number of bytes that the saved frame pointer takes on the stack. */
int fp_size = frame_pointer_needed * UNITS_PER_WORD;
/* The number of bytes that the saved registers, excluding the frame
pointer, take on the stack. */
int saved_regs_size = 0;
/* The number of bytes that the locals takes on the stack. */
int frame_size = round_frame_size (get_frame_size ());
int regno;
for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
if (WORD_REG_USED (regno))
saved_regs_size += UNITS_PER_WORD;
/* Adjust saved_regs_size because the above loop took the frame
pointer int account. */
saved_regs_size -= fp_size;
switch (to)
{
case HARD_FRAME_POINTER_REGNUM:
switch (from)
{
case ARG_POINTER_REGNUM:
return pc_size + fp_size;
case RETURN_ADDRESS_POINTER_REGNUM:
return fp_size;
case FRAME_POINTER_REGNUM:
return -saved_regs_size;
default:
gcc_unreachable ();
}
break;
case STACK_POINTER_REGNUM:
switch (from)
{
case ARG_POINTER_REGNUM:
return pc_size + saved_regs_size + frame_size;
case RETURN_ADDRESS_POINTER_REGNUM:
return saved_regs_size + frame_size;
case FRAME_POINTER_REGNUM:
return frame_size;
default:
gcc_unreachable ();
}
break;
default:
gcc_unreachable ();
}
gcc_unreachable ();
}
/* Worker function for RETURN_ADDR_RTX. */
rtx
h8300_return_addr_rtx (int count, rtx frame)
{
rtx ret;
if (count == 0)
ret = gen_rtx_MEM (Pmode,
gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
else if (flag_omit_frame_pointer)
return (rtx) 0;
else
ret = gen_rtx_MEM (Pmode,
memory_address (Pmode,
plus_constant (Pmode, frame,
UNITS_PER_WORD)));
set_mem_alias_set (ret, get_frame_alias_set ());
return ret;
}
machine_mode
h8300_select_cc_mode (enum rtx_code cond, rtx op0, rtx op1)
{
if (op1 == const0_rtx
&& (cond == EQ || cond == NE || cond == LT || cond == GE)
&& (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
|| GET_CODE (op0) == NEG || GET_CODE (op0) == AND
|| GET_CODE (op0) == IOR || GET_CODE (op0) == XOR
|| GET_CODE (op0) == NOT || GET_CODE (op0) == ASHIFT
|| GET_CODE (op0) == ASHIFTRT || GET_CODE (op0) == LSHIFTRT
|| GET_CODE (op0) == MULT || GET_CODE (op0) == SYMBOL_REF
|| GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND
|| REG_P (op0) || MEM_P (op0)))
return CCZNmode;
return CCmode;
}
/* Given that X occurs in an address of the form (plus X constant),
return the part of X that is expected to be a register. There are
four kinds of addressing mode to recognize:
@(dd,Rn)
@(dd,RnL.b)
@(dd,Rn.w)
@(dd,ERn.l)
If SIZE is nonnull, and the address is one of the last three forms,
set *SIZE to the index multiplication factor. Set it to 0 for
plain @(dd,Rn) addresses.
MODE is the mode of the value being accessed. It can be VOIDmode
if the address is known to be valid, but its mode is unknown. */
static rtx
h8300_get_index (rtx x, machine_mode mode, int *size)
{
int dummy, factor;
if (size == 0)
size = &dummy;
factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
if (TARGET_H8300SX
&& factor <= 4
&& (mode == VOIDmode
|| GET_MODE_CLASS (mode) == MODE_INT
|| GET_MODE_CLASS (mode) == MODE_FLOAT))
{
if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
{
/* When accessing byte-sized values, the index can be
a zero-extended QImode or HImode register. */
*size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
return XEXP (x, 0);
}
else
{
/* We're looking for addresses of the form:
(mult X I)
or (mult (zero_extend X) I)
where I is the size of the operand being accessed.
The canonical form of the second expression is:
(and (mult (subreg X) I) J)
where J == GET_MODE_MASK (GET_MODE (X)) * I. */
rtx index;
if (GET_CODE (x) == AND
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& (factor == 0
|| INTVAL (XEXP (x, 1)) == 0xff * factor
|| INTVAL (XEXP (x, 1)) == 0xffff * factor))
{
index = XEXP (x, 0);
*size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
}
else
{
index = x;
*size = 4;
}
if (GET_CODE (index) == MULT
&& GET_CODE (XEXP (index, 1)) == CONST_INT
&& (factor == 0 || factor == INTVAL (XEXP (index, 1))))
return XEXP (index, 0);
}
}
*size = 0;
return x;
}
/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
On the H8/300, the predecrement and postincrement address depend thus
(the amount of decrement or increment being the length of the operand). */
static bool
h8300_mode_dependent_address_p (const_rtx addr,
addr_space_t as ATTRIBUTE_UNUSED)
{
if (GET_CODE (addr) == PLUS
&& h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
return true;
return false;
}
static const h8300_length_table addb_length_table =
{
/* #xx Rs @aa @Rs @xx */
{ 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
{ 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
{ 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
{ 6, 4, 4, 4, 6 } /* add.b xx,@xx */
};
static const h8300_length_table addw_length_table =
{
/* #xx Rs @aa @Rs @xx */
{ 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
{ 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
{ 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
{ 4, 4, 4, 4, 6 } /* add.w xx,@xx */
};
static const h8300_length_table addl_length_table =
{
/* #xx Rs @aa @Rs @xx */
{ 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
{ 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
{ 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
{ 4, 4, 6, 6, 6 } /* add.l xx,@xx */
};
#define logicb_length_table addb_length_table
#define logicw_length_table addw_length_table
static const h8300_length_table logicl_length_table =
{
/* #xx Rs @aa @Rs @xx */
{ 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
{ 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
{ 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
{ 4, 4, 6, 6, 6 } /* and.l xx,@xx */
};
static const h8300_length_table movb_length_table =
{
/* #xx Rs @aa @Rs @xx */
{ 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
{ 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
{ 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
{ 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
};
#define movw_length_table movb_length_table
static const h8300_length_table movl_length_table =
{
/* #xx Rs @aa @Rs @xx */
{ 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
{ 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
{ 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
{ 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
};
/* Return the size of the given address or displacement constant. */
static unsigned int
h8300_constant_length (rtx constant)
{
/* Check for (@d:16,Reg). */
if (GET_CODE (constant) == CONST_INT
&& IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
return 2;
/* Check for (@d:16,Reg) in cases where the displacement is
an absolute address. */
if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
return 2;
return 4;
}
/* Return the size of a displacement field in address ADDR, which should
have the form (plus X constant). SIZE is the number of bytes being
accessed. */
static unsigned int
h8300_displacement_length (rtx addr, int size)
{
rtx offset;
offset = XEXP (addr, 1);
/* Check for @(d:2,Reg). */
if (register_operand (XEXP (addr, 0), VOIDmode)
&& GET_CODE (offset) == CONST_INT
&& (INTVAL (offset) == size
|| INTVAL (offset) == size * 2
|| INTVAL (offset) == size * 3))
return 0;
return h8300_constant_length (offset);
}
/* Store the class of operand OP in *OPCLASS and return the length of any
extra operand fields. SIZE is the number of bytes in OP. OPCLASS
can be null if only the length is needed. */
static unsigned int
h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
{
enum h8300_operand_class dummy;
if (opclass == 0)
opclass = &dummy;
if (CONSTANT_P (op))
{
*opclass = H8OP_IMMEDIATE;
/* Byte-sized immediates are stored in the opcode fields. */
if (size == 1)
return 0;
/* If this is a 32-bit instruction, see whether the constant
will fit into a 16-bit immediate field. */
if (TARGET_H8300SX
&& size == 4
&& GET_CODE (op) == CONST_INT
&& IN_RANGE (INTVAL (op), 0, 0xffff))
return 2;
return size;
}
else if (GET_CODE (op) == MEM)
{
op = XEXP (op, 0);
if (CONSTANT_P (op))
{
*opclass = H8OP_MEM_ABSOLUTE;
return h8300_constant_length (op);
}
else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
{
*opclass = H8OP_MEM_COMPLEX;
return h8300_displacement_length (op, size);
}
else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
{
*opclass = H8OP_MEM_COMPLEX;
return 0;
}
else if (register_operand (op, VOIDmode))
{
*opclass = H8OP_MEM_BASE;
return 0;
}
}
gcc_assert (register_operand (op, VOIDmode));
*opclass = H8OP_REGISTER;
return 0;
}
/* Return the length of the instruction described by TABLE given that
its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
and OP2 must be an h8300_src_operand. */
static unsigned int
h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
{
enum h8300_operand_class op1_class, op2_class;
unsigned int size, immediate_length;
size = GET_MODE_SIZE (GET_MODE (op1));
immediate_length = (h8300_classify_operand (op1, size, &op1_class)
+ h8300_classify_operand (op2, size, &op2_class));
return immediate_length + (*table)[op1_class - 1][op2_class];
}
/* Return the length of a unary instruction such as neg or not given that
its operand is OP. */
unsigned int
h8300_unary_length (rtx op)
{
enum h8300_operand_class opclass;
unsigned int size, operand_length;
size = GET_MODE_SIZE (GET_MODE (op));
operand_length = h8300_classify_operand (op, size, &opclass);
switch (opclass)
{
case H8OP_REGISTER:
return 2;
case H8OP_MEM_BASE:
return (size == 4 ? 6 : 4);
case H8OP_MEM_ABSOLUTE:
return operand_length + (size == 4 ? 6 : 4);
case H8OP_MEM_COMPLEX:
return operand_length + 6;
default:
gcc_unreachable ();
}
}
/* Likewise short immediate instructions such as add.w #xx:3,OP. */
static unsigned int
h8300_short_immediate_length (rtx op)
{
enum h8300_operand_class opclass;
unsigned int size, operand_length;
size = GET_MODE_SIZE (GET_MODE (op));
operand_length = h8300_classify_operand (op, size, &opclass);
switch (opclass)
{
case H8OP_REGISTER:
return 2;
case H8OP_MEM_BASE:
case H8OP_MEM_ABSOLUTE:
case H8OP_MEM_COMPLEX:
return 4 + operand_length;
default:
gcc_unreachable ();
}
}
/* Likewise bitfield load and store instructions. */
static unsigned int
h8300_bitfield_length (rtx op, rtx op2)
{
enum h8300_operand_class opclass;
unsigned int size, operand_length;
if (GET_CODE (op) == REG)
op = op2;
gcc_assert (GET_CODE (op) != REG);
size = GET_MODE_SIZE (GET_MODE (op));
operand_length = h8300_classify_operand (op, size, &opclass);
switch (opclass)
{
case H8OP_MEM_BASE:
case H8OP_MEM_ABSOLUTE:
case H8OP_MEM_COMPLEX:
return 4 + operand_length;
default:
gcc_unreachable ();
}
}
/* Calculate the length of general binary instruction INSN using TABLE. */
static unsigned int
h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
{
rtx set;
rtx pattern;
if (GET_CODE (insn) != INSN)
gcc_unreachable ();
pattern = PATTERN (insn);
if (GET_CODE (pattern) == PARALLEL
&& GET_CODE (XVECEXP (pattern, 0, 0)) == SET
&& GET_CODE (SET_SRC (XVECEXP (pattern, 0, 0))) == COMPARE)
set = XVECEXP (pattern, 0, 1);
else
set = single_set (insn);
gcc_assert (set);
if (BINARY_P (SET_SRC (set)))
return h8300_length_from_table (XEXP (SET_SRC (set), 0),
XEXP (SET_SRC (set), 1), table);
else
{
gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
XEXP (XEXP (SET_SRC (set), 1), 1),
table);
}
}
/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
memory reference and either (1) it has the form @(d:16,Rn) or
(2) its address has the code given by INC_CODE. */
static bool
h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
{
rtx addr;
unsigned int size;
if (GET_CODE (op) != MEM)
return false;
addr = XEXP (op, 0);
size = GET_MODE_SIZE (GET_MODE (op));
if (size != 1 && size != 2)
return false;
return (GET_CODE (addr) == inc_code
|| (GET_CODE (addr) == PLUS
&& GET_CODE (XEXP (addr, 0)) == REG
&& h8300_displacement_length (addr, size) == 2));
}
/* Calculate the length of move instruction INSN using the given length
table. Although the tables are correct for most cases, there is some
irregularity in the length of mov.b and mov.w. The following forms:
mov @ERs+, Rd
mov @(d:16,ERs), Rd
mov Rs, @-ERd
mov Rs, @(d:16,ERd)
are two bytes shorter than most other "mov Rs, @complex" or
"mov @complex,Rd" combinations. */
static unsigned int
h8300_move_length (rtx *operands, const h8300_length_table *table)
{
unsigned int size;
size = h8300_length_from_table (operands[0], operands[1], table);
if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
size -= 2;
if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
size -= 2;
return size;
}
/* Return the length of a mova instruction with the given operands.
DEST is the register destination, SRC is the source address and
OFFSET is the 16-bit or 32-bit displacement. */
static unsigned int
h8300_mova_length (rtx dest, rtx src, rtx offset)
{
unsigned int size;
size = (2
+ h8300_constant_length (offset)
+ h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
size += 2;
return size;
}
/* Compute the length of INSN based on its length_table attribute.
OPERANDS is the array of its operands. */
unsigned int
h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
{
switch (get_attr_length_table (insn))
{
case LENGTH_TABLE_NONE:
gcc_unreachable ();
case LENGTH_TABLE_ADD:
if (GET_MODE (operands[0]) == QImode)
return h8300_binary_length (insn, &addb_length_table);
else if (GET_MODE (operands[0]) == HImode)
return h8300_binary_length (insn, &addw_length_table);
else if (GET_MODE (operands[0]) == SImode)
return h8300_binary_length (insn, &addl_length_table);
gcc_unreachable ();
case LENGTH_TABLE_LOGICB:
return h8300_binary_length (insn, &logicb_length_table);
case LENGTH_TABLE_MOVB:
return h8300_move_length (operands, &movb_length_table);
case LENGTH_TABLE_MOVW:
return h8300_move_length (operands, &movw_length_table);
case LENGTH_TABLE_MOVL:
return h8300_move_length (operands, &movl_length_table);
case LENGTH_TABLE_MOVA:
return h8300_mova_length (operands[0], operands[1], operands[2]);
case LENGTH_TABLE_MOVA_ZERO:
return h8300_mova_length (operands[0], operands[1], const0_rtx);
case LENGTH_TABLE_UNARY:
return h8300_unary_length (operands[0]);
case LENGTH_TABLE_MOV_IMM4:
return 2 + h8300_classify_operand (operands[0], 0, 0);
case LENGTH_TABLE_SHORT_IMMEDIATE:
return h8300_short_immediate_length (operands[0]);
case LENGTH_TABLE_BITFIELD:
return h8300_bitfield_length (operands[0], operands[1]);
case LENGTH_TABLE_BITBRANCH:
return h8300_bitfield_length (operands[1], operands[2]) - 2;
default:
gcc_unreachable ();
}
}
/* Return true if LHS and RHS are memory references that can be mapped
to the same h8sx assembly operand. LHS appears as the destination of
an instruction and RHS appears as a source.
Three cases are allowed:
- RHS is @+Rn or @-Rn, LHS is @Rn
- RHS is @Rn, LHS is @Rn+ or @Rn-
- RHS and LHS have the same address and neither has side effects. */
bool
h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
{
if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
{
rhs = XEXP (rhs, 0);
lhs = XEXP (lhs, 0);
if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
return rtx_equal_p (XEXP (rhs, 0), lhs);
if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
return rtx_equal_p (rhs, XEXP (lhs, 0));
if (rtx_equal_p (rhs, lhs))
return true;
}
return false;
}
/* Return true if OPERANDS[1] can be mapped to the same assembly
operand as OPERANDS[0]. */
bool
h8300_operands_match_p (rtx *operands)
{
if (register_operand (operands[0], VOIDmode)
&& register_operand (operands[1], VOIDmode))
return true;
if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
return true;
return false;
}
/* Return the length of mov instruction. */
unsigned int
compute_mov_length (rtx *operands)
{
/* If the mov instruction involves a memory operand, we compute the
length, assuming the largest addressing mode is used, and then
adjust later in the function. Otherwise, we compute and return
the exact length in one step. */
machine_mode mode = GET_MODE (operands[0]);
rtx dest = operands[0];
rtx src = operands[1];
rtx addr;
if (GET_CODE (src) == MEM)
addr = XEXP (src, 0);
else if (GET_CODE (dest) == MEM)
addr = XEXP (dest, 0);
else
addr = NULL_RTX;
unsigned int base_length;
switch (mode)
{
case E_QImode:
if (addr == NULL_RTX)
return 2;
/* The eightbit addressing is available only in QImode, so
go ahead and take care of it. */
if (h8300_eightbit_constant_address_p (addr))
return 2;
base_length = 8;
break;
case E_HImode:
if (addr == NULL_RTX)
{
if (REG_P (src))
return 2;
if (src == const0_rtx)
return 2;
return 4;
}
base_length = 8;
break;
case E_SImode:
if (addr == NULL_RTX)
{
if (REG_P (src))
{
if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
return 4;
else
return 2;
}
if (GET_CODE (src) == CONST_INT)
{
int val = INTVAL (src);
if (val == 0)
return 2;
if (val == (val & 0x00ff) || val == (val & 0xff00))
return 4;
switch (val & 0xffffffff)
{
case 0xffffffff:
case 0xfffffffe:
case 0xfffffffc:
case 0x0000ffff:
case 0x0000fffe:
case 0xffff0000:
case 0xfffe0000:
case 0x00010000:
case 0x00020000:
return 4;
}
}
return 6;
}
base_length = 10;
break;
case E_SFmode:
if (addr == NULL_RTX)
{
if (REG_P (src))
return 2;
if (satisfies_constraint_G (src))
return 2;
return 6;
}
base_length = 10;
break;
default:
gcc_unreachable ();
}
/* Adjust the length based on the addressing mode used.
Specifically, we subtract the difference between the actual
length and the longest one, which is @(d:24,ERs). */
/* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
if (GET_CODE (addr) == PRE_DEC
|| GET_CODE (addr) == POST_INC)
return base_length - 6;
/* @ERs and @ERd are 6 bytes shorter than the longest. */
if (GET_CODE (addr) == REG)
return base_length - 6;
/* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
longest. */
if (GET_CODE (addr) == PLUS
&& GET_CODE (XEXP (addr, 0)) == REG
&& GET_CODE (XEXP (addr, 1)) == CONST_INT
&& INTVAL (XEXP (addr, 1)) > -32768
&& INTVAL (XEXP (addr, 1)) < 32767)
return base_length - 4;
/* @aa:16 is 4 bytes shorter than the longest. */
if (h8300_tiny_constant_address_p (addr))
return base_length - 4;
/* @aa:24 is 2 bytes shorter than the longest. */
if (CONSTANT_P (addr))
return base_length - 2;
return base_length;
}
/* Output an addition insn. */
const char *
output_plussi (rtx *operands, bool need_flags)
{
machine_mode mode = GET_MODE (operands[0]);
gcc_assert (mode == SImode);
if (GET_CODE (operands[2]) == CONST_INT
&& register_operand (operands[1], VOIDmode))
{
HOST_WIDE_INT intval = INTVAL (operands[2]);
if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
return "add.l\t%S2,%S0";
if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
return "sub.l\t%G2,%S0";
/* See if we can finish with 2 bytes. */
switch ((unsigned int) intval & 0xffffffff)
{
/* INC/DEC set the flags, but adds/subs do not. So if we
need flags, use the former and not the latter. */
case 0x00000001:
if (need_flags)
return "inc.l\t#1,%S0";
else
return "adds\t%2,%S0";
case 0x00000002:
if (need_flags)
return "inc.l\t#2,%S0";
else
return "adds\t%2,%S0";
case 0xffffffff:
if (need_flags)
return "dec.l\t#1,%S0";
else
return "subs\t%G2,%S0";
case 0xfffffffe:
if (need_flags)
return "dec.l\t#2,%S0";
else
return "subs\t%G2,%S0";
/* These six cases have optimized paths when we do not
need flags. Otherwise we let them fallthru. */
case 0x00000004:
if (!need_flags)
return "adds\t%2,%S0";
/* FALLTHRU */
case 0xfffffffc:
if (!need_flags)
return "subs\t%G2,%S0";
/* FALLTHRU */
case 0x00010000:
case 0x00020000:
if (!need_flags)
{
operands[2] = GEN_INT (intval >> 16);
return "inc.w\t%2,%e0";
}
/* FALLTHRU */
case 0xffff0000:
case 0xfffe0000:
if (!need_flags)
{
operands[2] = GEN_INT (intval >> 16);
return "dec.w\t%G2,%e0";
}
/* FALLTHRU */
}
/* See if we can finish with 4 bytes. */
if ((intval & 0xffff) == 0)
{
operands[2] = GEN_INT (intval >> 16);
return "add.w\t%2,%e0";
}
}
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
return "sub.l\t%S2,%S0";
}
return "add.l\t%S2,%S0";
}
/* ??? It would be much easier to add the h8sx stuff if a single function
classified the addition as either inc/dec, adds/subs, add.w or add.l. */
/* Compute the length of an addition insn. */
unsigned int
compute_plussi_length (rtx *operands, bool need_flags)
{
machine_mode mode = GET_MODE (operands[0]);
gcc_assert (mode == SImode);
if (GET_CODE (operands[2]) == CONST_INT
&& register_operand (operands[1], VOIDmode))
{
HOST_WIDE_INT intval = INTVAL (operands[2]);
if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
return 2;
if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
return 2;
/* See if we can finish with 2 bytes. */
switch ((unsigned int) intval & 0xffffffff)
{
case 0x00000001:
case 0x00000002:
return 2;
case 0x00000004:
if (need_flags)
return 6;
else
return 2;
case 0xffffffff:
case 0xfffffffe:
return 2;
case 0xfffffffc:
if (need_flags)
return 6;
else
return 2;
case 0x00010000:
case 0x00020000:
if (!need_flags)
return 2;
/* FALLTHRU */
case 0xffff0000:
case 0xfffe0000:
if (!need_flags)
return 2;
/* FALLTHRU */
}
/* See if we can finish with 4 bytes. */
if ((intval & 0xffff) == 0)
return 4;
}
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
return h8300_length_from_table (operands[0],
GEN_INT (-INTVAL (operands[2])),
&addl_length_table);
else
return h8300_length_from_table (operands[0], operands[2],
&addl_length_table);
}
/* Compute which flag bits are valid after an addition insn. */
enum attr_old_cc
compute_plussi_cc (rtx *operands)
{
machine_mode mode = GET_MODE (operands[0]);
gcc_assert (mode == SImode);
if (GET_CODE (operands[2]) == CONST_INT
&& register_operand (operands[1], VOIDmode))
{
HOST_WIDE_INT intval = INTVAL (operands[2]);
if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
return OLD_CC_SET_ZN;
if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
return OLD_CC_SET_ZN;
/* See if we can finish with 2 bytes. */
switch ((unsigned int) intval & 0xffffffff)
{
case 0x00000001:
case 0x00000002:
case 0x00000004:
return OLD_CC_NONE_0HIT;
case 0xffffffff:
case 0xfffffffe:
case 0xfffffffc:
return OLD_CC_NONE_0HIT;
case 0x00010000:
case 0x00020000:
return OLD_CC_CLOBBER;
case 0xffff0000:
case 0xfffe0000:
return OLD_CC_CLOBBER;
}
/* See if we can finish with 4 bytes. */
if ((intval & 0xffff) == 0)
return OLD_CC_CLOBBER;
}
return OLD_CC_SET_ZN;
}
/* Output a logical insn. */
const char *
output_logical_op (machine_mode mode, rtx_code code, rtx *operands, rtx_insn *insn)
{
/* Pretend that every byte is affected if both operands are registers. */
const unsigned HOST_WIDE_INT intval =
(unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
/* Always use the full instruction if the
first operand is in memory. It is better
to use define_splits to generate the shorter
sequence where valid. */
&& register_operand (operands[1], VOIDmode)
? INTVAL (operands[2]) : 0x55555555);
/* The determinant of the algorithm. If we perform an AND, 0
affects a bit. Otherwise, 1 affects a bit. */
const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
/* Break up DET into pieces. */
const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
int lower_half_easy_p = 0;
int upper_half_easy_p = 0;
/* The name of an insn. */
const char *opname;
char insn_buf[100];
/* INSN is the current insn, we examine its overall form to see if we're
supposed to set or clobber the condition codes.
This is important to know. If we are setting condition codes, then we
must do the operation in MODE and not in some smaller size.
The key is to look at the second object in the PARALLEL. If it is not
a CLOBBER, then we care about the condition codes. */
rtx pattern = PATTERN (insn);
gcc_assert (GET_CODE (pattern) == PARALLEL);
rtx second_op = XVECEXP (pattern, 0, 1);
bool cc_meaningful = (GET_CODE (second_op) != CLOBBER);
switch (code)
{
case AND:
opname = "and";
break;
case IOR:
opname = "or";
break;
case XOR:
opname = "xor";
break;
default:
gcc_unreachable ();
}
switch (mode)
{
case E_QImode:
sprintf (insn_buf, "%s.b\t%%X2,%%X0", opname);
output_asm_insn (insn_buf, operands);
break;
case E_HImode:
/* First, see if we can (or must) finish with one insn. */
if (cc_meaningful
|| (b0 != 0 && b1 != 0))
{
sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
output_asm_insn (insn_buf, operands);
}
else
{
/* Take care of the lower byte. */
if (b0 != 0)
{
sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
output_asm_insn (insn_buf, operands);
}
/* Take care of the upper byte. */
if (b1 != 0)
{
sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
output_asm_insn (insn_buf, operands);
}
}
break;
case E_SImode:
/* Determine if the lower half can be taken care of in no more
than two bytes. */
lower_half_easy_p = (b0 == 0
|| b1 == 0
|| (code != IOR && w0 == 0xffff));
/* Determine if the upper half can be taken care of in no more
than two bytes. */
upper_half_easy_p = ((code != IOR && w1 == 0xffff)
|| (code == AND && w1 == 0xff00));
/* Check if doing everything with one insn is no worse than
using multiple insns. */
if (cc_meaningful
|| (w0 != 0 && w1 != 0
&& !(lower_half_easy_p && upper_half_easy_p)
&& !(code == IOR && w1 == 0xffff
&& (w0 & 0x8000) != 0 && lower_half_easy_p)))
{
sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
output_asm_insn (insn_buf, operands);
}
else
{
/* Take care of the lower and upper words individually. For
each word, we try different methods in the order of
1) the special insn (in case of AND or XOR),
2) the word-wise insn, and
3) The byte-wise insn. */
if (w0 == 0xffff && (code != IOR))
output_asm_insn ((code == AND)
? "sub.w\t%f0,%f0" : "not.w\t%f0",
operands);
else if ((b0 != 0) && (b1 != 0))
{
sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
output_asm_insn (insn_buf, operands);
}
else
{
if (b0 != 0)
{
sprintf (insn_buf, "%s\t%%w2,%%w0", opname</