)]}'
{
  "commit": "7e88b4e76418b131268802ccba5f74cf1835fc66",
  "tree": "7cdd99e240cfbd8ac44dc754246562d74a483418",
  "parents": [
    "787c7e0c01f091291edeb2471367119ca6f438e7"
  ],
  "author": {
    "name": "Jin Ma",
    "email": "jinma@linux.alibaba.com",
    "time": "Sat Sep 05 10:07:33 2026 -0600"
  },
  "committer": {
    "name": "Jeff Law",
    "email": "jeffreyalaw@gmail.com",
    "time": "Sat Sep 05 10:07:33 2026 -0600"
  },
  "message": "[PATCH v2] RISC-V: Fix overlapping vd/vs2 allocation for vector crypto [PR126196]\n\nThe RISC-V Vector Crypto specification reserves encodings where the\nvd register group overlaps vs2 for vsm3me.vv, vsm3c.vi, vaes*.vs and\nvsm4r.vs.  It also reserves encodings where vd overlaps either vs1 or\nvs2 for vsha2ms.vv, vsha2ch.vv and vsha2cl.vv.\n\nUse early-clobber destination constraints for the affected patterns.\nSelect those constraints by UNSPEC where patterns are shared, keeping\nlegal overlap for vghsh.vv, vaeskf2.vi, vgmul.vv and the .vv forms of\nAES and SM4.\n\n\tPR target/126196\n\ngcc/ChangeLog:\n\n\t* config/riscv/vector-crypto.md (vv_ins_con): New int attribute.\n\t(vv_ins1_con): Likewise.\n\t(vi_ins1_con): Likewise.\n\t(@pred_v\u003cvv_ins1_name\u003e\u003cmode\u003e): Use vv_ins1_con.\n\t(@pred_crypto_vv\u003cvv_ins_name\u003e\u003cins_type\u003e\u003cmode\u003e): Use vv_ins_con.\n\t(@pred_vi\u003cvi_ins1_name\u003e\u003cmode\u003e_nomaskedoff_scalar): Use vi_ins1_con.\n\t(@pred_vsm3me\u003cmode\u003e): Mark the destination as early-clobber.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/pr126196-1.c: New test.\n\t* gcc.target/riscv/pr126196-2.c: New test.\n\t* gcc.target/riscv/pr126196-3.c: New test.\n\t* gcc.target/riscv/pr126196-4.c: New test.\n",
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