; Options of Andes NDS32 cpu for GNU compiler
; Copyright (C) 2012-2022 Free Software Foundation, Inc.
; Contributed by Andes Technology Corporation.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it
; under the terms of the GNU General Public License as published
; by the Free Software Foundation; either version 3, or (at your
; option) any later version.
;
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; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; <http://www.gnu.org/licenses/>.

HeaderInclude
config/nds32/nds32-opts.h

; ---------------------------------------------------------------
; The following options are designed for aliasing and compatibility options.

EB
Target RejectNegative Alias(mbig-endian)
Generate code in big-endian mode.

EL
Target RejectNegative Alias(mlittle-endian)
Generate code in little-endian mode.

mfp-as-gp
Target RejectNegative Alias(mforce-fp-as-gp)
Force performing fp-as-gp optimization.

mno-fp-as-gp
Target RejectNegative Alias(mforbid-fp-as-gp)
Forbid performing fp-as-gp optimization.

; ---------------------------------------------------------------

mabi=
Target RejectNegative Joined Enum(abi_type) Var(nds32_abi) Init(TARGET_DEFAULT_ABI)
Specify which ABI type to generate code for: 2, 2fp+.

Enum
Name(abi_type) Type(enum abi_type)
Known ABIs (for use with the -mabi= option):

EnumValue
Enum(abi_type) String(2) Value(NDS32_ABI_V2)

EnumValue
Enum(abi_type) String(2fp+) Value(NDS32_ABI_V2_FP_PLUS)

mfloat-abi=soft
Target RejectNegative Alias(mabi=, 2)
Specify use soft floating point ABI which mean alias to -mabi=2.

mfloat-abi=hard
Target RejectNegative Alias(mabi=, 2fp+)
Specify use soft floating point ABI which mean alias to -mabi=2fp+.

; ---------------------------------------------------------------

mreduced-regs
Target RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
Use reduced-set registers for register allocation.

mfull-regs
Target RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
Use full-set registers for register allocation.

; ---------------------------------------------------------------

malways-align
Target Mask(ALWAYS_ALIGN)
Always align function entry, jump target and return address.

malign-functions
Target Mask(ALIGN_FUNCTION)
Align function entry to 4 byte.

mbig-endian
Target Undocumented RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
Generate code in big-endian mode.

mlittle-endian
Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
Generate code in little-endian mode.

mforce-fp-as-gp
Target Undocumented Mask(FORCE_FP_AS_GP)
Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization.

mforbid-fp-as-gp
Target Undocumented Mask(FORBID_FP_AS_GP)
Forbid using $fp to access static and global variables.  This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'.

mict-model=
Target Undocumented RejectNegative Joined Enum(nds32_ict_model_type) Var(nds32_ict_model) Init(ICT_MODEL_SMALL)
Specify the address generation strategy for ICT call's code model.

Enum
Name(nds32_ict_model_type) Type(enum nds32_ict_model_type)
Known cmodel types (for use with the -mict-model= option):

EnumValue
Enum(nds32_ict_model_type) String(small) Value(ICT_MODEL_SMALL)

EnumValue
Enum(nds32_ict_model_type) String(large) Value(ICT_MODEL_LARGE)

mcmov
Target Mask(CMOV)
Generate conditional move instructions.

mhw-abs
Target Mask(HW_ABS)
Generate hardware abs instructions.

mext-perf
Target Mask(EXT_PERF)
Generate performance extension instructions.

mext-perf2
Target Mask(EXT_PERF2)
Generate performance extension version 2 instructions.

mext-string
Target Mask(EXT_STRING)
Generate string extension instructions.

mext-dsp
Target Mask(EXT_DSP)
Generate DSP extension instructions.

mv3push
Target Mask(V3PUSH)
Generate v3 push25/pop25 instructions.

m16-bit
Target Mask(16_BIT)
Generate 16-bit instructions.

mrelax-hint
Target Mask(RELAX_HINT)
Insert relax hint for linker to do relaxation.

mvh
Target Mask(VH) Condition(!TARGET_LINUX_ABI)
Enable Virtual Hosting support.

misr-vector-size=
Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
Specify the size of each interrupt vector, which must be 4 or 16.

misr-secure=
Target RejectNegative Joined UInteger Var(nds32_isr_secure_level) Init(0)
Specify the security level of c-isr for the whole file.

mcache-block-size=
Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE)
Specify the size of each cache block, which must be a power of 2 between 4 and 512.

march=
Target RejectNegative Joined Enum(nds32_arch_type) Var(nds32_arch_option) Init(ARCH_V3)
Specify the name of the target architecture.

Enum
Name(nds32_arch_type) Type(enum nds32_arch_type)
Known arch types (for use with the -march= option):

EnumValue
Enum(nds32_arch_type) String(v2) Value(ARCH_V2)

EnumValue
Enum(nds32_arch_type) String(v3) Value(ARCH_V3)

EnumValue
Enum(nds32_arch_type) String(v3j) Value(ARCH_V3J)

EnumValue
Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M)

EnumValue
Enum(nds32_arch_type) String(v3f) Value(ARCH_V3F)

EnumValue
Enum(nds32_arch_type) String(v3s) Value(ARCH_V3S)

mcpu=
Target RejectNegative Joined Enum(nds32_cpu_type) Var(nds32_cpu_option) Init(CPU_N9)
Specify the cpu for pipeline model.

Enum
Name(nds32_cpu_type) Type(enum nds32_cpu_type)
Known cpu types (for use with the -mcpu= option):

EnumValue
Enum(nds32_cpu_type) String(n6) Value(CPU_N6)

EnumValue
Enum(nds32_cpu_type) String(n650) Value(CPU_N6)

EnumValue
Enum(nds32_cpu_type) String(n7) Value(CPU_N7)

EnumValue
Enum(nds32_cpu_type) String(n705) Value(CPU_N7)

EnumValue
Enum(nds32_cpu_type) String(n8) Value(CPU_N8)

EnumValue
Enum(nds32_cpu_type) String(n801) Value(CPU_N8)

EnumValue
Enum(nds32_cpu_type) String(sn8) Value(CPU_N8)

EnumValue
Enum(nds32_cpu_type) String(sn801) Value(CPU_N8)

EnumValue
Enum(nds32_cpu_type) String(s8) Value(CPU_N8)

EnumValue
Enum(nds32_cpu_type) String(s801) Value(CPU_N8)

EnumValue
Enum(nds32_cpu_type) String(e8) Value(CPU_E8)

EnumValue
Enum(nds32_cpu_type) String(e801) Value(CPU_E8)

EnumValue
Enum(nds32_cpu_type) String(n820) Value(CPU_E8)

EnumValue
Enum(nds32_cpu_type) String(s830) Value(CPU_E8)

EnumValue
Enum(nds32_cpu_type) String(e830) Value(CPU_E8)

EnumValue
Enum(nds32_cpu_type) String(n9) Value(CPU_N9)

EnumValue
Enum(nds32_cpu_type) String(n903) Value(CPU_N9)

EnumValue
Enum(nds32_cpu_type) String(n903a) Value(CPU_N9)

EnumValue
Enum(nds32_cpu_type) String(n968) Value(CPU_N9)

EnumValue
Enum(nds32_cpu_type) String(n968a) Value(CPU_N9)

EnumValue
Enum(nds32_cpu_type) String(n10) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(n1033) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(n1033a) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(n1033-fpu) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(n1033-spu) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(n1068) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(n1068a) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(n1068-fpu) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(n1068a-fpu) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(n1068-spu) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(n1068a-spu) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(d10) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(d1088) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(d1088-fpu) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) String(d1088-spu) Value(CPU_N10)

EnumValue
Enum(nds32_cpu_type) Undocumented String(graywolf) Value(CPU_GRAYWOLF)

EnumValue
Enum(nds32_cpu_type) String(n15) Value(CPU_GRAYWOLF)

EnumValue
Enum(nds32_cpu_type) String(d15) Value(CPU_GRAYWOLF)

EnumValue
Enum(nds32_cpu_type) String(n15s) Value(CPU_GRAYWOLF)

EnumValue
Enum(nds32_cpu_type) String(d15s) Value(CPU_GRAYWOLF)

EnumValue
Enum(nds32_cpu_type) String(n15f) Value(CPU_GRAYWOLF)

EnumValue
Enum(nds32_cpu_type) String(d15f) Value(CPU_GRAYWOLF)

EnumValue
Enum(nds32_cpu_type) String(n12) Value(CPU_N12)

EnumValue
Enum(nds32_cpu_type) String(n1213) Value(CPU_N12)

EnumValue
Enum(nds32_cpu_type) String(n1233) Value(CPU_N12)

EnumValue
Enum(nds32_cpu_type) String(n1233-fpu) Value(CPU_N12)

EnumValue
Enum(nds32_cpu_type) String(n1233-spu) Value(CPU_N12)

EnumValue
Enum(nds32_cpu_type) String(n13) Value(CPU_N13)

EnumValue
Enum(nds32_cpu_type) String(n1337) Value(CPU_N13)

EnumValue
Enum(nds32_cpu_type) String(n1337-fpu) Value(CPU_N13)

EnumValue
Enum(nds32_cpu_type) String(n1337-spu) Value(CPU_N13)

EnumValue
Enum(nds32_cpu_type) String(simple) Value(CPU_SIMPLE)

mconfig-fpu=
Target RejectNegative Joined Enum(float_reg_number) Var(nds32_fp_regnum) Init(TARGET_CONFIG_FPU_DEFAULT)
Specify a fpu configuration value from 0 to 7; 0-3 is as FPU spec says, and 4-7 is corresponding to 0-3.

Enum
Name(float_reg_number) Type(enum float_reg_number)
Known floating-point number of registers (for use with the -mconfig-fpu= option):

EnumValue
Enum(float_reg_number) String(0) Value(NDS32_CONFIG_FPU_0)

EnumValue
Enum(float_reg_number) String(1) Value(NDS32_CONFIG_FPU_1)

EnumValue
Enum(float_reg_number) String(2) Value(NDS32_CONFIG_FPU_2)

EnumValue
Enum(float_reg_number) String(3) Value(NDS32_CONFIG_FPU_3)

EnumValue
Enum(float_reg_number) String(4) Value(NDS32_CONFIG_FPU_4)

EnumValue
Enum(float_reg_number) String(5) Value(NDS32_CONFIG_FPU_5)

EnumValue
Enum(float_reg_number) String(6) Value(NDS32_CONFIG_FPU_6)

EnumValue
Enum(float_reg_number) String(7) Value(NDS32_CONFIG_FPU_7)

mconfig-mul=
Target RejectNegative Joined Enum(nds32_mul_type) Var(nds32_mul_config) Init(MUL_TYPE_FAST_1)
Specify configuration of instruction mul: fast1, fast2 or slow. The default is fast1.

Enum
Name(nds32_mul_type) Type(enum nds32_mul_type)

EnumValue
Enum(nds32_mul_type) String(fast) Value(MUL_TYPE_FAST_1)

EnumValue
Enum(nds32_mul_type) String(fast1) Value(MUL_TYPE_FAST_1)

EnumValue
Enum(nds32_mul_type) String(fast2) Value(MUL_TYPE_FAST_2)

EnumValue
Enum(nds32_mul_type) String(slow) Value(MUL_TYPE_SLOW)

mconfig-register-ports=
Target RejectNegative Joined Enum(nds32_register_ports) Var(nds32_register_ports_config) Init(REG_PORT_3R2W)
Specify how many read/write ports for n9/n10 cores.  The value should be 3r2w or 2r1w.

Enum
Name(nds32_register_ports) Type(enum nds32_register_ports)

EnumValue
Enum(nds32_register_ports) String(3r2w) Value(REG_PORT_3R2W)

EnumValue
Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W)

mctor-dtor
Target
Enable constructor/destructor feature.

mrelax
Target
Guide linker to relax instructions.

mext-fpu-fma
Target Mask(EXT_FPU_FMA)
Generate floating-point multiply-accumulation instructions.

mext-fpu-sp
Target Mask(FPU_SINGLE)
Generate single-precision floating-point instructions.

mext-fpu-dp
Target Mask(FPU_DOUBLE)
Generate double-precision floating-point instructions.

mforce-no-ext-dsp
Target Undocumented Mask(FORCE_NO_EXT_DSP)
Force disable hardware loop, even use -mext-dsp.

msched-prolog-epilog
Target Var(flag_sched_prolog_epilog) Init(0)
Permit scheduling of a function's prologue and epilogue sequence.

mret-in-naked-func
Target Var(flag_ret_in_naked_func) Init(1)
Generate return instruction in naked function.

malways-save-lp
Target Var(flag_always_save_lp) Init(0)
Always save $lp in the stack.

munaligned-access
Target Var(flag_unaligned_access) Init(0)
Enable unaligned word and halfword accesses to packed data.

minline-asm-r15
Target Var(flag_inline_asm_r15) Init(0)
Allow use r15 for inline ASM.