gnu /
gcc /
a62d957342e3e9ee9bda812f737279f1166e03ba RISC-V: Optimize RVV epilogue logic.
Sometimes "step1 -= scalable_frame" will cause adjust equal to
zero. And it will generate additional redundant instruction
"addi sp,sp,0". Add checking segement to skip that case.
This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
Do not emit useless add sp, sp, 0 instrutions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.
2 files changed
