blob: 3621cb501c70c80f7f134f5d6cacf83adc8fcdc2 [file] [log] [blame]
/* Subroutines used to generate function prologues and epilogues
on IBM RS/6000.
Copyright (C) 1991-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "rtl.h"
#include "tree.h"
#include "memmodel.h"
#include "df.h"
#include "tm_p.h"
#include "ira.h"
#include "print-tree.h"
#include "varasm.h"
#include "explow.h"
#include "expr.h"
#include "output.h"
#include "tree-pass.h"
#include "rtx-vector-builder.h"
#include "predict.h"
#include "target.h"
#include "stringpool.h"
#include "attribs.h"
#include "except.h"
#include "langhooks.h"
#include "optabs.h"
#include "diagnostic-core.h"
#include "alias.h"
#include "rs6000-internal.h"
static int rs6000_ra_ever_killed (void);
static void is_altivec_return_reg (rtx, void *);
static bool rs6000_save_toc_in_prologue_p (void);
static rs6000_stack_t stack_info;
/* Set if HARD_FRAM_POINTER_REGNUM is really needed. */
static bool frame_pointer_needed_indeed = false;
/* Label number of label created for -mrelocatable, to call to so we can
get the address of the GOT section */
int rs6000_pic_labelno = 0;
#ifndef TARGET_PROFILE_KERNEL
#define TARGET_PROFILE_KERNEL 0
#endif
/* Function to init struct machine_function.
This will be called, via a pointer variable,
from push_function_context. */
struct machine_function *
rs6000_init_machine_status (void)
{
stack_info.reload_completed = 0;
return ggc_cleared_alloc<machine_function> ();
}
/* This page contains routines that are used to determine what the
function prologue and epilogue code will do and write them out. */
/* Determine whether the REG is really used. */
bool
save_reg_p (int reg)
{
if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
{
/* When calling eh_return, we must return true for all the cases
where conditional_register_usage marks the PIC offset reg
call used or fixed. */
if (crtl->calls_eh_return
&& ((DEFAULT_ABI == ABI_V4 && flag_pic)
|| (DEFAULT_ABI == ABI_DARWIN && flag_pic)
|| (TARGET_TOC && TARGET_MINIMAL_TOC)))
return true;
/* We need to mark the PIC offset register live for the same
conditions as it is set up in rs6000_emit_prologue, or
otherwise it won't be saved before we clobber it. */
if (TARGET_TOC && TARGET_MINIMAL_TOC
&& !constant_pool_empty_p ())
return true;
if (DEFAULT_ABI == ABI_V4
&& (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
&& df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
return true;
if (DEFAULT_ABI == ABI_DARWIN
&& flag_pic && crtl->uses_pic_offset_table)
return true;
}
return !call_used_or_fixed_reg_p (reg) && df_regs_ever_live_p (reg);
}
/* Return the first fixed-point register that is required to be
saved. 32 if none. */
int
first_reg_to_save (void)
{
int first_reg;
/* Find lowest numbered live register. */
for (first_reg = 13; first_reg <= 31; first_reg++)
if (save_reg_p (first_reg))
break;
return first_reg;
}
/* Similar, for FP regs. */
int
first_fp_reg_to_save (void)
{
int first_reg;
/* Find lowest numbered live register. */
for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
if (save_reg_p (first_reg))
break;
return first_reg;
}
/* Similar, for AltiVec regs. */
static int
first_altivec_reg_to_save (void)
{
int i;
/* Stack frame remains as is unless we are in AltiVec ABI. */
if (! TARGET_ALTIVEC_ABI)
return LAST_ALTIVEC_REGNO + 1;
/* On Darwin, the unwind routines are compiled without
TARGET_ALTIVEC, and use save_world to save/restore the
altivec registers when necessary. */
if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
&& ! TARGET_ALTIVEC)
return FIRST_ALTIVEC_REGNO + 20;
/* Find lowest numbered live register. */
for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
if (save_reg_p (i))
break;
return i;
}
/* Return a 32-bit mask of the AltiVec registers we need to set in
VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
the 32-bit word is 0. */
static unsigned int
compute_vrsave_mask (void)
{
unsigned int i, mask = 0;
/* On Darwin, the unwind routines are compiled without
TARGET_ALTIVEC, and use save_world to save/restore the
call-saved altivec registers when necessary. */
if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
&& ! TARGET_ALTIVEC)
mask |= 0xFFF;
/* First, find out if we use _any_ altivec registers. */
for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
if (df_regs_ever_live_p (i))
mask |= ALTIVEC_REG_BIT (i);
if (mask == 0)
return mask;
/* Next, remove the argument registers from the set. These must
be in the VRSAVE mask set by the caller, so we don't need to add
them in again. More importantly, the mask we compute here is
used to generate CLOBBERs in the set_vrsave insn, and we do not
wish the argument registers to die. */
for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
mask &= ~ALTIVEC_REG_BIT (i);
/* Similarly, remove the return value from the set. */
{
bool yes = false;
diddle_return_value (is_altivec_return_reg, &yes);
if (yes)
mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
}
return mask;
}
/* For a very restricted set of circumstances, we can cut down the
size of prologues/epilogues by calling our own save/restore-the-world
routines. */
static void
compute_save_world_info (rs6000_stack_t *info)
{
info->world_save_p = 1;
info->world_save_p
= (WORLD_SAVE_P (info)
&& DEFAULT_ABI == ABI_DARWIN
&& !cfun->has_nonlocal_label
&& info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
&& info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
&& info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
&& info->cr_save_p);
/* This will not work in conjunction with sibcalls. Make sure there
are none. (This check is expensive, but seldom executed.) */
if (WORLD_SAVE_P (info))
{
rtx_insn *insn;
for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
if (CALL_P (insn) && SIBLING_CALL_P (insn))
{
info->world_save_p = 0;
break;
}
}
if (WORLD_SAVE_P (info))
{
/* Even if we're not touching VRsave, make sure there's room on the
stack for it, if it looks like we're calling SAVE_WORLD, which
will attempt to save it. */
info->vrsave_size = 4;
/* If we are going to save the world, we need to save the link register too. */
info->lr_save_p = 1;
/* "Save" the VRsave register too if we're saving the world. */
if (info->vrsave_mask == 0)
info->vrsave_mask = compute_vrsave_mask ();
/* Because the Darwin register save/restore routines only handle
F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
check. */
gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
&& (info->first_altivec_reg_save
>= FIRST_SAVED_ALTIVEC_REGNO));
}
return;
}
static void
is_altivec_return_reg (rtx reg, void *xyes)
{
bool *yes = (bool *) xyes;
if (REGNO (reg) == ALTIVEC_ARG_RETURN)
*yes = true;
}
/* Return whether REG is a global user reg or has been specifed by
-ffixed-REG. We should not restore these, and so cannot use
lmw or out-of-line restore functions if there are any. We also
can't save them (well, emit frame notes for them), because frame
unwinding during exception handling will restore saved registers. */
static bool
fixed_reg_p (int reg)
{
/* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
backend sets it, overriding anything the user might have given. */
if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
&& ((DEFAULT_ABI == ABI_V4 && flag_pic)
|| (DEFAULT_ABI == ABI_DARWIN && flag_pic)
|| (TARGET_TOC && TARGET_MINIMAL_TOC)))
return false;
return fixed_regs[reg];
}
/* Determine the strategy for savings/restoring registers. */
enum {
SAVE_MULTIPLE = 0x1,
SAVE_INLINE_GPRS = 0x2,
SAVE_INLINE_FPRS = 0x4,
SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
SAVE_INLINE_VRS = 0x20,
REST_MULTIPLE = 0x100,
REST_INLINE_GPRS = 0x200,
REST_INLINE_FPRS = 0x400,
REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
REST_INLINE_VRS = 0x1000
};
static int
rs6000_savres_strategy (rs6000_stack_t *info,
bool using_static_chain_p)
{
int strategy = 0;
/* Select between in-line and out-of-line save and restore of regs.
First, all the obvious cases where we don't use out-of-line. */
if (crtl->calls_eh_return
|| cfun->machine->ra_need_lr)
strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
| SAVE_INLINE_GPRS | REST_INLINE_GPRS
| SAVE_INLINE_VRS | REST_INLINE_VRS);
if (info->first_gp_reg_save == 32)
strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
if (info->first_fp_reg_save == 64)
strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
/* Define cutoff for using out-of-line functions to save registers. */
if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
{
if (!optimize_size)
{
strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
}
else
{
/* Prefer out-of-line restore if it will exit. */
if (info->first_fp_reg_save > 61)
strategy |= SAVE_INLINE_FPRS;
if (info->first_gp_reg_save > 29)
{
if (info->first_fp_reg_save == 64)
strategy |= SAVE_INLINE_GPRS;
else
strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
}
if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
}
}
else if (DEFAULT_ABI == ABI_DARWIN)
{
if (info->first_fp_reg_save > 60)
strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
if (info->first_gp_reg_save > 29)
strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
}
else
{
gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
|| info->first_fp_reg_save > 61)
strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
}
/* Don't bother to try to save things out-of-line if r11 is occupied
by the static chain. It would require too much fiddling and the
static chain is rarely used anyway. FPRs are saved w.r.t the stack
pointer on Darwin, and AIX uses r1 or r12. */
if (using_static_chain_p
&& (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
| SAVE_INLINE_GPRS
| SAVE_INLINE_VRS);
/* Don't ever restore fixed regs. That means we can't use the
out-of-line register restore functions if a fixed reg is in the
range of regs restored. */
if (!(strategy & REST_INLINE_FPRS))
for (int i = info->first_fp_reg_save; i < 64; i++)
if (fixed_regs[i])
{
strategy |= REST_INLINE_FPRS;
break;
}
/* We can only use the out-of-line routines to restore fprs if we've
saved all the registers from first_fp_reg_save in the prologue.
Otherwise, we risk loading garbage. Of course, if we have saved
out-of-line then we know we haven't skipped any fprs. */
if ((strategy & SAVE_INLINE_FPRS)
&& !(strategy & REST_INLINE_FPRS))
for (int i = info->first_fp_reg_save; i < 64; i++)
if (!save_reg_p (i))
{
strategy |= REST_INLINE_FPRS;
break;
}
/* Similarly, for altivec regs. */
if (!(strategy & REST_INLINE_VRS))
for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
if (fixed_regs[i])
{
strategy |= REST_INLINE_VRS;
break;
}
if ((strategy & SAVE_INLINE_VRS)
&& !(strategy & REST_INLINE_VRS))
for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
if (!save_reg_p (i))
{
strategy |= REST_INLINE_VRS;
break;
}
/* info->lr_save_p isn't yet set if the only reason lr needs to be
saved is an out-of-line save or restore. Set up the value for
the next test (excluding out-of-line gprs). */
bool lr_save_p = (info->lr_save_p
|| !(strategy & SAVE_INLINE_FPRS)
|| !(strategy & SAVE_INLINE_VRS)
|| !(strategy & REST_INLINE_FPRS)
|| !(strategy & REST_INLINE_VRS));
if (TARGET_MULTIPLE
&& !TARGET_POWERPC64
&& info->first_gp_reg_save < 31
&& !(flag_shrink_wrap
&& flag_shrink_wrap_separate
&& optimize_function_for_speed_p (cfun)))
{
int count = 0;
for (int i = info->first_gp_reg_save; i < 32; i++)
if (save_reg_p (i))
count++;
if (count <= 1)
/* Don't use store multiple if only one reg needs to be
saved. This can occur for example when the ABI_V4 pic reg
(r30) needs to be saved to make calls, but r31 is not
used. */
strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
else
{
/* Prefer store multiple for saves over out-of-line
routines, since the store-multiple instruction will
always be smaller. */
strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
/* The situation is more complicated with load multiple.
We'd prefer to use the out-of-line routines for restores,
since the "exit" out-of-line routines can handle the
restore of LR and the frame teardown. However if doesn't
make sense to use the out-of-line routine if that is the
only reason we'd need to save LR, and we can't use the
"exit" out-of-line gpr restore if we have saved some
fprs; In those cases it is advantageous to use load
multiple when available. */
if (info->first_fp_reg_save != 64 || !lr_save_p)
strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
}
}
/* Using the "exit" out-of-line routine does not improve code size
if using it would require lr to be saved and if only saving one
or two gprs. */
else if (!lr_save_p && info->first_gp_reg_save > 29)
strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
/* Don't ever restore fixed regs. */
if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
for (int i = info->first_gp_reg_save; i < 32; i++)
if (fixed_reg_p (i))
{
strategy |= REST_INLINE_GPRS;
strategy &= ~REST_MULTIPLE;
break;
}
/* We can only use load multiple or the out-of-line routines to
restore gprs if we've saved all the registers from
first_gp_reg_save. Otherwise, we risk loading garbage.
Of course, if we have saved out-of-line or used stmw then we know
we haven't skipped any gprs. */
if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
&& (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
for (int i = info->first_gp_reg_save; i < 32; i++)
if (!save_reg_p (i))
{
strategy |= REST_INLINE_GPRS;
strategy &= ~REST_MULTIPLE;
break;
}
if (TARGET_ELF && TARGET_64BIT)
{
if (!(strategy & SAVE_INLINE_FPRS))
strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
else if (!(strategy & SAVE_INLINE_GPRS)
&& info->first_fp_reg_save == 64)
strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
}
else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
return strategy;
}
/* Calculate the stack information for the current function. This is
complicated by having two separate calling sequences, the AIX calling
sequence and the V.4 calling sequence.
AIX (and Darwin/Mac OS X) stack frames look like:
32-bit 64-bit
SP----> +---------------------------------------+
| back chain to caller | 0 0
+---------------------------------------+
| saved CR | 4 8 (8-11)
+---------------------------------------+
| saved LR | 8 16
+---------------------------------------+
| reserved for compilers | 12 24
+---------------------------------------+
| reserved for binders | 16 32
+---------------------------------------+
| saved TOC pointer | 20 40
+---------------------------------------+
| Parameter save area (+padding*) (P) | 24 48
+---------------------------------------+
| Alloca space (A) | 24+P etc.
+---------------------------------------+
| Local variable space (L) | 24+P+A
+---------------------------------------+
| Float/int conversion temporary (X) | 24+P+A+L
+---------------------------------------+
| Save area for AltiVec registers (W) | 24+P+A+L+X
+---------------------------------------+
| AltiVec alignment padding (Y) | 24+P+A+L+X+W
+---------------------------------------+
| Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
+---------------------------------------+
| Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
+---------------------------------------+
| Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
+---------------------------------------+
old SP->| back chain to caller's caller |
+---------------------------------------+
* If the alloca area is present, the parameter save area is
padded so that the former starts 16-byte aligned.
The required alignment for AIX configurations is two words (i.e., 8
or 16 bytes).
The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
SP----> +---------------------------------------+
| Back chain to caller | 0
+---------------------------------------+
| Save area for CR | 8
+---------------------------------------+
| Saved LR | 16
+---------------------------------------+
| Saved TOC pointer | 24
+---------------------------------------+
| Parameter save area (+padding*) (P) | 32
+---------------------------------------+
| Optional ROP hash slot (R) | 32+P
+---------------------------------------+
| Alloca space (A) | 32+P+R
+---------------------------------------+
| Local variable space (L) | 32+P+R+A
+---------------------------------------+
| Save area for AltiVec registers (W) | 32+P+R+A+L
+---------------------------------------+
| AltiVec alignment padding (Y) | 32+P+R+A+L+W
+---------------------------------------+
| Save area for GP registers (G) | 32+P+R+A+L+W+Y
+---------------------------------------+
| Save area for FP registers (F) | 32+P+R+A+L+W+Y+G
+---------------------------------------+
old SP->| back chain to caller's caller | 32+P+R+A+L+W+Y+G+F
+---------------------------------------+
* If the alloca area is present, the parameter save area is
padded so that the former starts 16-byte aligned.
V.4 stack frames look like:
SP----> +---------------------------------------+
| back chain to caller | 0
+---------------------------------------+
| caller's saved LR | 4
+---------------------------------------+
| Parameter save area (+padding*) (P) | 8
+---------------------------------------+
| Alloca space (A) | 8+P
+---------------------------------------+
| Varargs save area (V) | 8+P+A
+---------------------------------------+
| Local variable space (L) | 8+P+A+V
+---------------------------------------+
| Float/int conversion temporary (X) | 8+P+A+V+L
+---------------------------------------+
| Save area for AltiVec registers (W) | 8+P+A+V+L+X
+---------------------------------------+
| AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
+---------------------------------------+
| Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
+---------------------------------------+
| saved CR (C) | 8+P+A+V+L+X+W+Y+Z
+---------------------------------------+
| Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
+---------------------------------------+
| Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
+---------------------------------------+
old SP->| back chain to caller's caller |
+---------------------------------------+
* If the alloca area is present and the required alignment is
16 bytes, the parameter save area is padded so that the
alloca area starts 16-byte aligned.
The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
given. (But note below and in sysv4.h that we require only 8 and
may round up the size of our stack frame anyways. The historical
reason is early versions of powerpc-linux which didn't properly
align the stack at program startup. A happy side-effect is that
-mno-eabi libraries can be used with -meabi programs.)
The EABI configuration defaults to the V.4 layout. However,
the stack alignment requirements may differ. If -mno-eabi is not
given, the required stack alignment is 8 bytes; if -mno-eabi is
given, the required alignment is 16 bytes. (But see V.4 comment
above.) */
#ifndef ABI_STACK_BOUNDARY
#define ABI_STACK_BOUNDARY STACK_BOUNDARY
#endif
rs6000_stack_t *
rs6000_stack_info (void)
{
/* We should never be called for thunks, we are not set up for that. */
gcc_assert (!cfun->is_thunk);
rs6000_stack_t *info = &stack_info;
int reg_size = TARGET_32BIT ? 4 : 8;
int ehrd_size;
int ehcr_size;
int save_align;
int first_gp;
HOST_WIDE_INT non_fixed_size;
bool using_static_chain_p;
if (reload_completed && info->reload_completed)
return info;
memset (info, 0, sizeof (*info));
info->reload_completed = reload_completed;
/* Select which calling sequence. */
info->abi = DEFAULT_ABI;
/* Calculate which registers need to be saved & save area size. */
info->first_gp_reg_save = first_reg_to_save ();
/* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
even if it currently looks like we won't. Reload may need it to
get at a constant; if so, it will have already created a constant
pool entry for it. */
if (((TARGET_TOC && TARGET_MINIMAL_TOC)
|| (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
|| (flag_pic && DEFAULT_ABI == ABI_DARWIN))
&& crtl->uses_const_pool
&& info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
else
first_gp = info->first_gp_reg_save;
info->gp_size = reg_size * (32 - first_gp);
info->first_fp_reg_save = first_fp_reg_to_save ();
info->fp_size = 8 * (64 - info->first_fp_reg_save);
info->first_altivec_reg_save = first_altivec_reg_to_save ();
info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
- info->first_altivec_reg_save);
/* Does this function call anything (apart from sibling calls)? */
info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
info->rop_hash_size = 0;
if (TARGET_POWER10
&& info->calls_p
&& DEFAULT_ABI == ABI_ELFv2
&& rs6000_rop_protect)
info->rop_hash_size = 8;
else if (rs6000_rop_protect && DEFAULT_ABI != ABI_ELFv2)
{
/* We can't check this in rs6000_option_override_internal since
DEFAULT_ABI isn't established yet. */
error ("%qs requires the ELFv2 ABI", "-mrop-protect");
}
/* Determine if we need to save the condition code registers. */
if (save_reg_p (CR2_REGNO)
|| save_reg_p (CR3_REGNO)
|| save_reg_p (CR4_REGNO))
{
info->cr_save_p = 1;
if (DEFAULT_ABI == ABI_V4)
info->cr_size = reg_size;
}
/* If the current function calls __builtin_eh_return, then we need
to allocate stack space for registers that will hold data for
the exception handler. */
if (crtl->calls_eh_return)
{
unsigned int i;
for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
continue;
ehrd_size = i * UNITS_PER_WORD;
}
else
ehrd_size = 0;
/* In the ELFv2 ABI, we also need to allocate space for separate
CR field save areas if the function calls __builtin_eh_return. */
if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
{
/* This hard-codes that we have three call-saved CR fields. */
ehcr_size = 3 * reg_size;
/* We do *not* use the regular CR save mechanism. */
info->cr_save_p = 0;
}
else
ehcr_size = 0;
/* Determine various sizes. */
info->reg_size = reg_size;
info->fixed_size = RS6000_SAVE_AREA;
info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
if (cfun->calls_alloca)
info->parm_size =
RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
else
info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
TARGET_ALTIVEC ? 16 : 8);
if (FRAME_GROWS_DOWNWARD)
info->vars_size
+= RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
ABI_STACK_BOUNDARY / BITS_PER_UNIT)
- (info->fixed_size + info->vars_size + info->parm_size);
if (TARGET_ALTIVEC_ABI)
info->vrsave_mask = compute_vrsave_mask ();
if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
info->vrsave_size = 4;
compute_save_world_info (info);
/* Calculate the offsets. */
switch (DEFAULT_ABI)
{
case ABI_NONE:
default:
gcc_unreachable ();
case ABI_AIX:
case ABI_ELFv2:
case ABI_DARWIN:
info->fp_save_offset = -info->fp_size;
info->gp_save_offset = info->fp_save_offset - info->gp_size;
if (TARGET_ALTIVEC_ABI)
{
info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
/* Align stack so vector save area is on a quadword boundary.
The padding goes above the vectors. */
if (info->altivec_size != 0)
info->altivec_padding_size = info->vrsave_save_offset & 0xF;
info->altivec_save_offset = info->vrsave_save_offset
- info->altivec_padding_size
- info->altivec_size;
gcc_assert (info->altivec_size == 0
|| info->altivec_save_offset % 16 == 0);
/* Adjust for AltiVec case. */
info->ehrd_offset = info->altivec_save_offset - ehrd_size;
/* Adjust for ROP protection. */
info->rop_hash_save_offset
= info->altivec_save_offset - info->rop_hash_size;
info->ehrd_offset -= info->rop_hash_size;
}
else
info->ehrd_offset = info->gp_save_offset - ehrd_size;
info->ehcr_offset = info->ehrd_offset - ehcr_size;
info->cr_save_offset = reg_size; /* first word when 64-bit. */
info->lr_save_offset = 2*reg_size;
break;
case ABI_V4:
info->fp_save_offset = -info->fp_size;
info->gp_save_offset = info->fp_save_offset - info->gp_size;
info->cr_save_offset = info->gp_save_offset - info->cr_size;
if (TARGET_ALTIVEC_ABI)
{
info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
/* Align stack so vector save area is on a quadword boundary. */
if (info->altivec_size != 0)
info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
info->altivec_save_offset = info->vrsave_save_offset
- info->altivec_padding_size
- info->altivec_size;
/* Adjust for AltiVec case. */
info->ehrd_offset = info->altivec_save_offset;
}
else
info->ehrd_offset = info->cr_save_offset;
info->ehrd_offset -= ehrd_size;
info->lr_save_offset = reg_size;
}
save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
info->save_size = RS6000_ALIGN (info->fp_size
+ info->gp_size
+ info->altivec_size
+ info->altivec_padding_size
+ info->rop_hash_size
+ ehrd_size
+ ehcr_size
+ info->cr_size
+ info->vrsave_size,
save_align);
non_fixed_size = info->vars_size + info->parm_size + info->save_size;
info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
ABI_STACK_BOUNDARY / BITS_PER_UNIT);
/* Determine if we need to save the link register. */
if (info->calls_p
|| ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
&& crtl->profile
&& !TARGET_PROFILE_KERNEL)
|| (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
#ifdef TARGET_RELOCATABLE
|| (DEFAULT_ABI == ABI_V4
&& (TARGET_RELOCATABLE || flag_pic > 1)
&& !constant_pool_empty_p ())
#endif
|| rs6000_ra_ever_killed ())
info->lr_save_p = 1;
using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
&& df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
&& call_used_or_fixed_reg_p (STATIC_CHAIN_REGNUM));
info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
if (!(info->savres_strategy & SAVE_INLINE_GPRS)
|| !(info->savres_strategy & SAVE_INLINE_FPRS)
|| !(info->savres_strategy & SAVE_INLINE_VRS)
|| !(info->savres_strategy & REST_INLINE_GPRS)
|| !(info->savres_strategy & REST_INLINE_FPRS)
|| !(info->savres_strategy & REST_INLINE_VRS))
info->lr_save_p = 1;
if (info->lr_save_p)
df_set_regs_ever_live (LR_REGNO, true);
/* Determine if we need to allocate any stack frame:
For AIX we need to push the stack if a frame pointer is needed
(because the stack might be dynamically adjusted), if we are
debugging, if we make calls, or if the sum of fp_save, gp_save,
and local variables are more than the space needed to save all
non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
+ 18*8 = 288 (GPR13 reserved).
For V.4 we don't have the stack cushion that AIX uses, but assume
that the debugger can handle stackless frames. */
if (info->calls_p)
info->push_p = 1;
else if (DEFAULT_ABI == ABI_V4)
info->push_p = non_fixed_size != 0;
else if (frame_pointer_needed)
info->push_p = 1;
else if (TARGET_XCOFF && write_symbols != NO_DEBUG && !flag_compare_debug)
info->push_p = 1;
else
info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
return info;
}
static void
debug_stack_info (rs6000_stack_t *info)
{
const char *abi_string;
if (! info)
info = rs6000_stack_info ();
fprintf (stderr, "\nStack information for function %s:\n",
((current_function_decl && DECL_NAME (current_function_decl))
? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
: "<unknown>"));
switch (info->abi)
{
default: abi_string = "Unknown"; break;
case ABI_NONE: abi_string = "NONE"; break;
case ABI_AIX: abi_string = "AIX"; break;
case ABI_ELFv2: abi_string = "ELFv2"; break;
case ABI_DARWIN: abi_string = "Darwin"; break;
case ABI_V4: abi_string = "V.4"; break;
}
fprintf (stderr, "\tABI = %5s\n", abi_string);
if (TARGET_ALTIVEC_ABI)
fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
if (info->first_gp_reg_save != 32)
fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
if (info->first_fp_reg_save != 64)
fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
info->first_altivec_reg_save);
if (info->lr_save_p)
fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
if (info->cr_save_p)
fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
if (info->vrsave_mask)
fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
if (info->push_p)
fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
if (info->calls_p)
fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
if (info->gp_size)
fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
if (info->fp_size)
fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
if (info->altivec_size)
fprintf (stderr, "\taltivec_save_offset = %5d\n",
info->altivec_save_offset);
if (info->vrsave_size)
fprintf (stderr, "\tvrsave_save_offset = %5d\n",
info->vrsave_save_offset);
if (info->rop_hash_size)
fprintf (stderr, "\trop_hash_save_offset = %5d\n",
info->rop_hash_save_offset);
if (info->lr_save_p)
fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
if (info->cr_save_p)
fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
if (info->varargs_save_offset)
fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
if (info->total_size)
fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
info->total_size);
if (info->vars_size)
fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
info->vars_size);
if (info->parm_size)
fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
if (info->fixed_size)
fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
if (info->gp_size)
fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
if (info->fp_size)
fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
if (info->altivec_size)
fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
if (info->vrsave_size)
fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
if (info->altivec_padding_size)
fprintf (stderr, "\taltivec_padding_size= %5d\n",
info->altivec_padding_size);
if (info->rop_hash_size)
fprintf (stderr, "\trop_hash_size = %5d\n", info->rop_hash_size);
if (info->cr_size)
fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
if (info->save_size)
fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
if (info->reg_size != 4)
fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
if (info->abi == ABI_DARWIN)
fprintf (stderr, "\tWORLD_SAVE_P = %5d\n", WORLD_SAVE_P(info));
fprintf (stderr, "\n");
}
rtx
rs6000_return_addr (int count, rtx frame)
{
/* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
if (count != 0
|| ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
{
cfun->machine->ra_needs_full_frame = 1;
if (count == 0)
/* FRAME is set to frame_pointer_rtx by the generic code, but that
is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
frame = stack_pointer_rtx;
rtx prev_frame_addr = memory_address (Pmode, frame);
rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
rtx lr_save_off = plus_constant (Pmode,
prev_frame, RETURN_ADDRESS_OFFSET);
rtx lr_save_addr = memory_address (Pmode, lr_save_off);
return gen_rtx_MEM (Pmode, lr_save_addr);
}
cfun->machine->ra_need_lr = 1;
return get_hard_reg_initial_val (Pmode, LR_REGNO);
}
/* Helper function for rs6000_function_ok_for_sibcall. */
bool
rs6000_decl_ok_for_sibcall (tree decl)
{
/* Sibcalls are always fine for the Darwin ABI. */
if (DEFAULT_ABI == ABI_DARWIN)
return true;
if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
{
/* A function compiled using the PC-relative addressing model does not
use a TOC pointer; nor is it guaranteed to preserve the value of
r2 for its caller's TOC. Such a function may make sibcalls to any
function, whether local or external, without restriction based on
TOC-save/restore rules. */
if (rs6000_pcrel_p ())
return true;
/* Otherwise, under the AIX or ELFv2 ABIs we can't allow sibcalls
to non-local functions, because the callee may not preserve the
TOC pointer, and there's no way to ensure we restore the TOC when
we return. */
if (!decl || DECL_EXTERNAL (decl) || DECL_WEAK (decl)
|| !(*targetm.binds_local_p) (decl))
return false;
/* A local sibcall from a function that preserves the TOC pointer
to a function that does not is invalid for the same reason. */
if (rs6000_fndecl_pcrel_p (decl))
return false;
return true;
}
/* With the secure-plt SYSV ABI we can't make non-local calls when
-fpic/PIC because the plt call stubs use r30. */
if (DEFAULT_ABI != ABI_V4
|| (TARGET_SECURE_PLT
&& flag_pic
&& (!decl || !((*targetm.binds_local_p) (decl)))))
return false;
return true;
}
/* Say whether a function is a candidate for sibcall handling or not. */
bool
rs6000_function_ok_for_sibcall (tree decl, tree exp)
{
tree fntype;
/* The sibcall epilogue may clobber the static chain register.
??? We could work harder and avoid that, but it's probably
not worth the hassle in practice. */
if (CALL_EXPR_STATIC_CHAIN (exp))
return false;
if (decl)
fntype = TREE_TYPE (decl);
else
fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
/* We can't do it if the called function has more vector parameters
than the current function; there's nowhere to put the VRsave code. */
if (TARGET_ALTIVEC_ABI
&& TARGET_ALTIVEC_VRSAVE
&& !(decl && decl == current_function_decl))
{
function_args_iterator args_iter;
tree type;
int nvreg = 0;
/* Functions with vector parameters are required to have a
prototype, so the argument type info must be available
here. */
FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
if (TREE_CODE (type) == VECTOR_TYPE
&& ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
nvreg++;
FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
if (TREE_CODE (type) == VECTOR_TYPE
&& ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
nvreg--;
if (nvreg > 0)
return false;
}
if (rs6000_decl_ok_for_sibcall (decl))
{
tree attr_list = TYPE_ATTRIBUTES (fntype);
if (!lookup_attribute ("longcall", attr_list)
|| lookup_attribute ("shortcall", attr_list))
return true;
}
return false;
}
static int
rs6000_ra_ever_killed (void)
{
rtx_insn *top;
rtx reg;
rtx_insn *insn;
if (cfun->is_thunk)
return 0;
if (cfun->machine->lr_save_state)
return cfun->machine->lr_save_state - 1;
/* regs_ever_live has LR marked as used if any sibcalls are present,
but this should not force saving and restoring in the
pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
clobbers LR, so that is inappropriate. */
/* Also, the prologue can generate a store into LR that
doesn't really count, like this:
move LR->R0
bcl to set PIC register
move LR->R31
move R0->LR
When we're called from the epilogue, we need to avoid counting
this as a store. */
push_topmost_sequence ();
top = get_insns ();
pop_topmost_sequence ();
reg = gen_rtx_REG (Pmode, LR_REGNO);
for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
{
if (INSN_P (insn))
{
if (CALL_P (insn))
{
if (!SIBLING_CALL_P (insn))
return 1;
}
else if (find_regno_note (insn, REG_INC, LR_REGNO))
return 1;
else if (set_of (reg, insn) != NULL_RTX
&& !prologue_epilogue_contains (insn))
return 1;
}
}
return 0;
}
/* Emit instructions needed to load the TOC register.
This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
a constant pool; or for SVR4 -fpic. */
void
rs6000_emit_load_toc_table (int fromprolog)
{
rtx dest;
dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
{
char buf[30];
rtx lab, tmp1, tmp2, got;
lab = gen_label_rtx ();
ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
if (flag_pic == 2)
{
got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
need_toc_init = 1;
}
else
got = rs6000_got_sym ();
tmp1 = tmp2 = dest;
if (!fromprolog)
{
tmp1 = gen_reg_rtx (Pmode);
tmp2 = gen_reg_rtx (Pmode);
}
emit_insn (gen_load_toc_v4_PIC_1 (lab));
emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
}
else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
{
emit_insn (gen_load_toc_v4_pic_si ());
emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
}
else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
{
char buf[30];
rtx temp0 = (fromprolog
? gen_rtx_REG (Pmode, 0)
: gen_reg_rtx (Pmode));
if (fromprolog)
{
rtx symF, symL;
ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
emit_insn (gen_load_toc_v4_PIC_1 (symF));
emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
}
else
{
rtx tocsym, lab;
tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
need_toc_init = 1;
lab = gen_label_rtx ();
emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
if (TARGET_LINK_STACK)
emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
}
emit_insn (gen_addsi3 (dest, temp0, dest));
}
else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
{
/* This is for AIX code running in non-PIC ELF32. */
rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
need_toc_init = 1;
emit_insn (gen_elf_high (dest, realsym));
emit_insn (gen_elf_low (dest, dest, realsym));
}
else
{
gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
if (TARGET_32BIT)
emit_insn (gen_load_toc_aix_si (dest));
else
emit_insn (gen_load_toc_aix_di (dest));
}
}
/* Emit instructions to restore the link register after determining where
its value has been stored. */
void
rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
{
rs6000_stack_t *info = rs6000_stack_info ();
rtx operands[2];
operands[0] = source;
operands[1] = scratch;
if (info->lr_save_p)
{
rtx frame_rtx = stack_pointer_rtx;
HOST_WIDE_INT sp_offset = 0;
rtx tmp;
if (frame_pointer_needed
|| cfun->calls_alloca
|| info->total_size > 32767)
{
tmp = gen_frame_mem (Pmode, frame_rtx);
emit_move_insn (operands[1], tmp);
frame_rtx = operands[1];
}
else if (info->push_p)
sp_offset = info->total_size;
tmp = plus_constant (Pmode, frame_rtx,
info->lr_save_offset + sp_offset);
tmp = gen_frame_mem (Pmode, tmp);
emit_move_insn (tmp, operands[0]);
}
else
emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
/* Freeze lr_save_p. We've just emitted rtl that depends on the
state of lr_save_p so any change from here on would be a bug. In
particular, stop rs6000_ra_ever_killed from considering the SET
of lr we may have added just above. */
cfun->machine->lr_save_state = info->lr_save_p + 1;
}
/* This returns nonzero if the current function uses the TOC. This is
determined by the presence of (use (unspec ... UNSPEC_TOC)), which
is generated by the ABI_V4 load_toc_* patterns.
Return 2 instead of 1 if the load_toc_* pattern is in the function
partition that doesn't start the function. */
#if TARGET_ELF
int
uses_TOC (void)
{
rtx_insn *insn;
int ret = 1;
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{
if (INSN_P (insn))
{
rtx pat = PATTERN (insn);
int i;
if (GET_CODE (pat) == PARALLEL)
for (i = 0; i < XVECLEN (pat, 0); i++)
{
rtx sub = XVECEXP (pat, 0, i);
if (GET_CODE (sub) == USE)
{
sub = XEXP (sub, 0);
if (GET_CODE (sub) == UNSPEC
&& XINT (sub, 1) == UNSPEC_TOC)
return ret;
}
}
}
else if (crtl->has_bb_partition
&& NOTE_P (insn)
&& NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
ret = 2;
}
return 0;
}
#endif
/* Issue assembly directives that create a reference to the given DWARF
FRAME_TABLE_LABEL from the current function section. */
void
rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
{
fprintf (asm_out_file, "\t.ref %s\n",
(* targetm.strip_name_encoding) (frame_table_label));
}
/* This ties together stack memory (MEM with an alias set of frame_alias_set)
and the change to the stack pointer. */
static void
rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
{
rtvec p;
int i;
rtx regs[3];
i = 0;
regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
if (hard_frame_needed)
regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
if (!(REGNO (fp) == STACK_POINTER_REGNUM
|| (hard_frame_needed
&& REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
regs[i++] = fp;
p = rtvec_alloc (i);
while (--i >= 0)
{
rtx mem = gen_frame_mem (BLKmode, regs[i]);
RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
}
emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
}
/* Allocate SIZE_INT bytes on the stack using a store with update style insn
and set the appropriate attributes for the generated insn. Return the
first insn which adjusts the stack pointer or the last insn before
the stack adjustment loop.
SIZE_INT is used to create the CFI note for the allocation.
SIZE_RTX is an rtx containing the size of the adjustment. Note that
since stacks grow to lower addresses its runtime value is -SIZE_INT.
ORIG_SP contains the backchain value that must be stored at *sp. */
static rtx_insn *
rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
{
rtx_insn *insn;
rtx size_rtx = GEN_INT (-size_int);
if (size_int > 32767)
{
rtx tmp_reg = gen_rtx_REG (Pmode, 0);
/* Need a note here so that try_split doesn't get confused. */
if (get_last_insn () == NULL_RTX)
emit_note (NOTE_INSN_DELETED);
insn = emit_move_insn (tmp_reg, size_rtx);
try_split (PATTERN (insn), insn, 0);
size_rtx = tmp_reg;
}
if (TARGET_32BIT)
insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
stack_pointer_rtx,
size_rtx,
orig_sp));
else
insn = emit_insn (gen_movdi_update_stack (stack_pointer_rtx,
stack_pointer_rtx,
size_rtx,
orig_sp));
rtx par = PATTERN (insn);
gcc_assert (GET_CODE (par) == PARALLEL);
rtx set = XVECEXP (par, 0, 0);
gcc_assert (GET_CODE (set) == SET);
rtx mem = SET_DEST (set);
gcc_assert (MEM_P (mem));
MEM_NOTRAP_P (mem) = 1;
set_mem_alias_set (mem, get_frame_alias_set ());
RTX_FRAME_RELATED_P (insn) = 1;
add_reg_note (insn, REG_FRAME_RELATED_EXPR,
gen_rtx_SET (stack_pointer_rtx,
gen_rtx_PLUS (Pmode,
stack_pointer_rtx,
GEN_INT (-size_int))));
/* Emit a blockage to ensure the allocation/probing insns are
not optimized, combined, removed, etc. Add REG_STACK_CHECK
note for similar reasons. */
if (flag_stack_clash_protection)
{
add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
emit_insn (gen_blockage ());
}
return insn;
}
static HOST_WIDE_INT
get_stack_clash_protection_probe_interval (void)
{
return (HOST_WIDE_INT_1U
<< param_stack_clash_protection_probe_interval);
}
static HOST_WIDE_INT
get_stack_clash_protection_guard_size (void)
{
return (HOST_WIDE_INT_1U
<< param_stack_clash_protection_guard_size);
}
/* Allocate ORIG_SIZE bytes on the stack and probe the newly
allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
COPY_REG, if non-null, should contain a copy of the original
stack pointer at exit from this function.
This is subtly different than the Ada probing in that it tries hard to
prevent attacks that jump the stack guard. Thus it is never allowed to
allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
space without a suitable probe. */
static rtx_insn *
rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
rtx copy_reg)
{
rtx orig_sp = copy_reg;
HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
/* Round the size down to a multiple of PROBE_INTERVAL. */
HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
/* If explicitly requested,
or the rounded size is not the same as the original size
or the rounded size is greater than a page,
then we will need a copy of the original stack pointer. */
if (rounded_size != orig_size
|| rounded_size > probe_interval
|| copy_reg)
{
/* If the caller did not request a copy of the incoming stack
pointer, then we use r0 to hold the copy. */
if (!copy_reg)
orig_sp = gen_rtx_REG (Pmode, 0);
emit_move_insn (orig_sp, stack_pointer_rtx);
}
/* There's three cases here.
One is a single probe which is the most common and most efficiently
implemented as it does not have to have a copy of the original
stack pointer if there are no residuals.
Second is unrolled allocation/probes which we use if there's just
a few of them. It needs to save the original stack pointer into a
temporary for use as a source register in the allocation/probe.
Last is a loop. This is the most uncommon case and least efficient. */
rtx_insn *retval = NULL;
if (rounded_size == probe_interval)
{
retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
}
else if (rounded_size <= 8 * probe_interval)
{
/* The ABI requires using the store with update insns to allocate
space and store the backchain into the stack
So we save the current stack pointer into a temporary, then
emit the store-with-update insns to store the saved stack pointer
into the right location in each new page. */
for (int i = 0; i < rounded_size; i += probe_interval)
{
rtx_insn *insn
= rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
/* Save the first stack adjustment in RETVAL. */
if (i == 0)
retval = insn;
}
dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
}
else
{
/* Compute the ending address. */
rtx end_addr
= copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
rtx rs = GEN_INT (-rounded_size);
rtx_insn *insn = gen_add3_insn (end_addr, stack_pointer_rtx, rs);
if (insn == NULL)
{
emit_move_insn (end_addr, rs);
insn = gen_add3_insn (end_addr, end_addr, stack_pointer_rtx);
gcc_assert (insn);
}
bool add_note = false;
if (!NONJUMP_INSN_P (insn) || NEXT_INSN (insn))
add_note = true;
else
{
rtx set = single_set (insn);
if (set == NULL_RTX
|| SET_DEST (set) != end_addr
|| GET_CODE (SET_SRC (set)) != PLUS
|| XEXP (SET_SRC (set), 0) != stack_pointer_rtx
|| XEXP (SET_SRC (set), 1) != rs)
add_note = true;
}
insn = emit_insn (insn);
/* Describe the effect of INSN to the CFI engine, unless it
is a single insn that describes it itself. */
if (add_note)
add_reg_note (insn, REG_FRAME_RELATED_EXPR,
gen_rtx_SET (end_addr,
gen_rtx_PLUS (Pmode, stack_pointer_rtx,
rs)));
RTX_FRAME_RELATED_P (insn) = 1;
/* Emit the loop. */
if (TARGET_64BIT)
retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
stack_pointer_rtx, orig_sp,
end_addr));
else
retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
stack_pointer_rtx, orig_sp,
end_addr));
RTX_FRAME_RELATED_P (retval) = 1;
/* Describe the effect of INSN to the CFI engine. */
add_reg_note (retval, REG_FRAME_RELATED_EXPR,
gen_rtx_SET (stack_pointer_rtx, end_addr));
/* Emit a blockage to ensure the allocation/probing insns are
not optimized, combined, removed, etc. Other cases handle this
within their call to rs6000_emit_allocate_stack_1. */
emit_insn (gen_blockage ());
dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
}
if (orig_size != rounded_size)
{
/* Allocate (and implicitly probe) any residual space. */
HOST_WIDE_INT residual = orig_size - rounded_size;
rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
/* If the residual was the only allocation, then we can return the
allocating insn. */
if (!retval)
retval = insn;
}
return retval;
}
/* Emit the correct code for allocating stack space, as insns.
If COPY_REG, make sure a copy of the old frame is left there.
The generated code may use hard register 0 as a temporary. */
static rtx_insn *
rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
{
rtx_insn *insn;
rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
rtx tmp_reg = gen_rtx_REG (Pmode, 0);
rtx todec = gen_int_mode (-size, Pmode);
if (INTVAL (todec) != -size)
{
warning (0, "stack frame too large");
emit_insn (gen_trap ());
return 0;
}
if (crtl->limit_stack)
{
if (REG_P (stack_limit_rtx)
&& REGNO (stack_limit_rtx) > 1
&& REGNO (stack_limit_rtx) <= 31)
{
rtx_insn *insn
= gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
gcc_assert (insn);
emit_insn (insn);
emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
}
else if (SYMBOL_REF_P (stack_limit_rtx)
&& TARGET_32BIT
&& DEFAULT_ABI == ABI_V4
&& !flag_pic)
{
rtx toload = gen_rtx_CONST (VOIDmode,
gen_rtx_PLUS (Pmode,
stack_limit_rtx,
GEN_INT (size)));
/* We cannot use r0 with elf_low. Lamely solve this problem by
moving registers around. */
rtx r11_reg = gen_rtx_REG (Pmode, 11);
emit_move_insn (tmp_reg, r11_reg);
emit_insn (gen_elf_high (r11_reg, toload));
emit_insn (gen_elf_low (r11_reg, r11_reg, toload));
emit_insn (gen_cond_trap (LTU, stack_reg, r11_reg, const0_rtx));
emit_move_insn (r11_reg, tmp_reg);
}
else
warning (0, "stack limit expression is not supported");
}
if (flag_stack_clash_protection)
{
if (size < get_stack_clash_protection_guard_size ())
dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
else
{
rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
copy_reg);
/* If we asked for a copy with an offset, then we still need add in
the offset. */
if (copy_reg && copy_off)
emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
return insn;
}
}
if (copy_reg)
{
if (copy_off != 0)
emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
else
emit_move_insn (copy_reg, stack_reg);
}
/* Since we didn't use gen_frame_mem to generate the MEM, grab
it now and set the alias set/attributes. The above gen_*_update
calls will generate a PARALLEL with the MEM set being the first
operation. */
insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
return insn;
}
#define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
#if PROBE_INTERVAL > 32768
#error Cannot use indexed addressing mode for stack probing
#endif
/* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
inclusive. These are offsets from the current stack pointer. */
static void
rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
{
/* See if we have a constant small number of probes to generate. If so,
that's the easy case. */
if (first + size <= 32768)
{
HOST_WIDE_INT i;
/* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
it exceeds SIZE. If only one probe is needed, this will not
generate any code. Then probe at FIRST + SIZE. */
for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
-(first + i)));
emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
-(first + size)));
}
/* Otherwise, do the same as above, but in a loop. Note that we must be
extra careful with variables wrapping around because we might be at
the very top (or the very bottom) of the address space and we have
to be able to handle this case properly; in particular, we use an
equality test for the loop condition. */
else
{
HOST_WIDE_INT rounded_size;
rtx r12 = gen_rtx_REG (Pmode, 12);
rtx r0 = gen_rtx_REG (Pmode, 0);
/* Sanity check for the addressing mode we're going to use. */
gcc_assert (first <= 32768);
/* Step 1: round SIZE to the previous multiple of the interval. */
rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
/* Step 2: compute initial and final value of the loop counter. */
/* TEST_ADDR = SP + FIRST. */
emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
-first)));
/* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
if (rounded_size > 32768)
{
emit_move_insn (r0, GEN_INT (-rounded_size));
emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
}
else
emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
-rounded_size)));
/* Step 3: the loop
do
{
TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
probe at TEST_ADDR
}
while (TEST_ADDR != LAST_ADDR)
probes at FIRST + N * PROBE_INTERVAL for values of N from 1
until it is equal to ROUNDED_SIZE. */
if (TARGET_64BIT)
emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
else
emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
/* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
that SIZE is equal to ROUNDED_SIZE. */
if (size != rounded_size)
emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
}
}
/* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
addresses, not offsets. */
static const char *
output_probe_stack_range_1 (rtx reg1, rtx reg2)
{
static int labelno = 0;
char loop_lab[32];
rtx xops[2];
ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
/* Loop. */
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
/* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
xops[0] = reg1;
xops[1] = GEN_INT (-PROBE_INTERVAL);
output_asm_insn ("addi %0,%0,%1", xops);
/* Probe at TEST_ADDR. */
xops[1] = gen_rtx_REG (Pmode, 0);
output_asm_insn ("stw %1,0(%0)", xops);
/* Test if TEST_ADDR == LAST_ADDR. */
xops[1] = reg2;
if (TARGET_64BIT)
output_asm_insn ("cmpd 0,%0,%1", xops);
else
output_asm_insn ("cmpw 0,%0,%1", xops);
/* Branch. */
fputs ("\tbne 0,", asm_out_file);
assemble_name_raw (asm_out_file, loop_lab);
fputc ('\n', asm_out_file);
return "";
}
/* This function is called when rs6000_frame_related is processing
SETs within a PARALLEL, and returns whether the REGNO save ought to
be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
for out-of-line register save functions, store multiple, and the
Darwin world_save. They may contain registers that don't really
need saving. */
static bool
interesting_frame_related_regno (unsigned int regno)
{
/* Saves apparently of r0 are actually saving LR. It doesn't make
sense to substitute the regno here to test save_reg_p (LR_REGNO).
We *know* LR needs saving, and dwarf2cfi.cc is able to deduce that
(set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
as frame related. */
if (regno == 0)
return true;
/* If we see CR2 then we are here on a Darwin world save. Saves of
CR2 signify the whole CR is being saved. This is a long-standing
ABI wart fixed by ELFv2. As for r0/lr there is no need to check
that CR needs to be saved. */
if (regno == CR2_REGNO)
return true;
/* Omit frame info for any user-defined global regs. If frame info
is supplied for them, frame unwinding will restore a user reg.
Also omit frame info for any reg we don't need to save, as that
bloats frame info and can cause problems with shrink wrapping.
Since global regs won't be seen as needing to be saved, both of
these conditions are covered by save_reg_p. */
return save_reg_p (regno);
}
/* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
addresses, not offsets.
REG2 contains the backchain that must be stored into *sp at each allocation.
This is subtly different than the Ada probing above in that it tries hard
to prevent attacks that jump the stack guard. Thus, it is never allowed
to allocate more than PROBE_INTERVAL bytes of stack space without a
suitable probe. */
static const char *
output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
{
static int labelno = 0;
char loop_lab[32];
rtx xops[3];
HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
/* This allocates and probes. */
xops[0] = reg1;
xops[1] = reg2;
xops[2] = GEN_INT (-probe_interval);
if (TARGET_64BIT)
output_asm_insn ("stdu %1,%2(%0)", xops);
else
output_asm_insn ("stwu %1,%2(%0)", xops);
/* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
xops[0] = reg1;
xops[1] = reg3;
if (TARGET_64BIT)
output_asm_insn ("cmpd 0,%0,%1", xops);
else
output_asm_insn ("cmpw 0,%0,%1", xops);
fputs ("\tbne 0,", asm_out_file);
assemble_name_raw (asm_out_file, loop_lab);
fputc ('\n', asm_out_file);
return "";
}
/* Wrapper around the output_probe_stack_range routines. */
const char *
output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
{
if (flag_stack_clash_protection)
return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
else
return output_probe_stack_range_1 (reg1, reg3);
}
/* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
is not NULL. It would be nice if dwarf2out_frame_debug_expr could
deduce these equivalences by itself so it wasn't necessary to hold
its hand so much. Don't be tempted to always supply d2_f_d_e with
the actual cfa register, ie. r31 when we are using a hard frame
pointer. That fails when saving regs off r1, and sched moves the
r31 setup past the reg saves. */
static rtx_insn *
rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
rtx reg2, rtx repl2)
{
rtx repl;
if (REGNO (reg) == STACK_POINTER_REGNUM)
{
gcc_checking_assert (val == 0);
repl = NULL_RTX;
}
else
repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
GEN_INT (val));
rtx pat = PATTERN (insn);
if (!repl && !reg2)
{
/* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
if (GET_CODE (pat) == PARALLEL)
for (int i = 0; i < XVECLEN (pat, 0); i++)
if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
{
rtx set = XVECEXP (pat, 0, i);
if (!REG_P (SET_SRC (set))
|| interesting_frame_related_regno (REGNO (SET_SRC (set))))
RTX_FRAME_RELATED_P (set) = 1;
}
RTX_FRAME_RELATED_P (insn) = 1;
return insn;
}
/* We expect that 'pat' is either a SET or a PARALLEL containing
SETs (and possibly other stuff). In a PARALLEL, all the SETs
are important so they all have to be marked RTX_FRAME_RELATED_P.
Call simplify_replace_rtx on the SETs rather than the whole insn
so as to leave the other stuff alone (for example USE of r12). */
set_used_flags (pat);
if (GET_CODE (pat) == SET)
{
if (repl)
pat = simplify_replace_rtx (pat, reg, repl);
if (reg2)
pat = simplify_replace_rtx (pat, reg2, repl2);
}
else if (GET_CODE (pat) == PARALLEL)
{
pat = shallow_copy_rtx (pat);
XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
for (int i = 0; i < XVECLEN (pat, 0); i++)
if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
{
rtx set = XVECEXP (pat, 0, i);
if (repl)
set = simplify_replace_rtx (set, reg, repl);
if (reg2)
set = simplify_replace_rtx (set, reg2, repl2);
XVECEXP (pat, 0, i) = set;
if (!REG_P (SET_SRC (set))
|| interesting_frame_related_regno (REGNO (SET_SRC (set))))
RTX_FRAME_RELATED_P (set) = 1;
}
}
else
gcc_unreachable ();
RTX_FRAME_RELATED_P (insn) = 1;
add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
return insn;
}
/* Returns an insn that has a vrsave set operation with the
appropriate CLOBBERs. */
static rtx
generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
{
int nclobs, i;
rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
clobs[0]
= gen_rtx_SET (vrsave,
gen_rtx_UNSPEC_VOLATILE (SImode,
gen_rtvec (2, reg, vrsave),
UNSPECV_SET_VRSAVE));
nclobs = 1;
/* We need to clobber the registers in the mask so the scheduler
does not move sets to VRSAVE before sets of AltiVec registers.
However, if the function receives nonlocal gotos, reload will set
all call saved registers live. We will end up with:
(set (reg 999) (mem))
(parallel [ (set (reg vrsave) (unspec blah))
(clobber (reg 999))])
The clobber will cause the store into reg 999 to be dead, and
flow will attempt to delete an epilogue insn. In this case, we
need an unspec use/set of the register. */
for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
{
if (!epiloguep || call_used_or_fixed_reg_p (i))
clobs[nclobs++] = gen_hard_reg_clobber (V4SImode, i);
else
{
rtx reg = gen_rtx_REG (V4SImode, i);
clobs[nclobs++]
= gen_rtx_SET (reg,
gen_rtx_UNSPEC (V4SImode,
gen_rtvec (1, reg), 27));
}
}
insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
for (i = 0; i < nclobs; ++i)
XVECEXP (insn, 0, i) = clobs[i];
return insn;
}
static rtx
gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
{
rtx addr, mem;
addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
mem = gen_frame_mem (GET_MODE (reg), addr);
return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
}
static rtx
gen_frame_load (rtx reg, rtx frame_reg, int offset)
{
return gen_frame_set (reg, frame_reg, offset, false);
}
static rtx
gen_frame_store (rtx reg, rtx frame_reg, int offset)
{
return gen_frame_set (reg, frame_reg, offset, true);
}
/* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
static rtx_insn *
emit_frame_save (rtx frame_reg, machine_mode mode,
unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
{
rtx reg;
/* Some cases that need register indexed addressing. */
gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
|| (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
reg = gen_rtx_REG (mode, regno);
rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
NULL_RTX, NULL_RTX);
}
/* Emit an offset memory reference suitable for a frame store, while
converting to a valid addressing mode. */
static rtx
gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
{
return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
}
#ifndef TARGET_FIX_AND_CONTINUE
#define TARGET_FIX_AND_CONTINUE 0
#endif
/* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
#define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
#define LAST_SAVRES_REGISTER 31
#define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
enum {
SAVRES_LR = 0x1,
SAVRES_SAVE = 0x2,
SAVRES_REG = 0x0c,
SAVRES_GPR = 0,
SAVRES_FPR = 4,
SAVRES_VR = 8
};
static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
/* Temporary holding space for an out-of-line register save/restore
routine name. */
static char savres_routine_name[30];
/* Return the name for an out-of-line register save/restore routine.
We are saving/restoring GPRs if GPR is true. */
static char *
rs6000_savres_routine_name (int regno, int sel)
{
const char *prefix = "";
const char *suffix = "";
/* Different targets are supposed to define
{SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
routine name could be defined with:
sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
This is a nice idea in practice, but in reality, things are
complicated in several ways:
- ELF targets have save/restore routines for GPRs.
- PPC64 ELF targets have routines for save/restore of GPRs that
differ in what they do with the link register, so having a set
prefix doesn't work. (We only use one of the save routines at
the moment, though.)
- PPC32 elf targets have "exit" versions of the restore routines
that restore the link register and can save some extra space.
These require an extra suffix. (There are also "tail" versions
of the restore routines and "GOT" versions of the save routines,
but we don't generate those at present. Same problems apply,
though.)
We deal with all this by synthesizing our own prefix/suffix and
using that for the simple sprintf call shown above. */
if (DEFAULT_ABI == ABI_V4)
{
if (TARGET_64BIT)
goto aix_names;
if ((sel & SAVRES_REG) == SAVRES_GPR)
prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
else if ((sel & SAVRES_REG) == SAVRES_FPR)
prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
else if ((sel & SAVRES_REG) == SAVRES_VR)
prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
else
abort ();
if ((sel & SAVRES_LR))
suffix = "_x";
}
else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
{
#if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
/* No out-of-line save/restore routines for GPRs on AIX. */
gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
#endif
aix_names:
if ((sel & SAVRES_REG) == SAVRES_GPR)
prefix = ((sel & SAVRES_SAVE)
? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
: ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
else if ((sel & SAVRES_REG) == SAVRES_FPR)
{
#if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
if ((sel & SAVRES_LR))
prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
else
#endif
{
prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
}
}
else if ((sel & SAVRES_REG) == SAVRES_VR)
prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
else
abort ();
}
if (DEFAULT_ABI == ABI_DARWIN)
{
/* The Darwin approach is (slightly) different, in order to be
compatible with code generated by the system toolchain. There is a
single symbol for the start of save sequence, and the code here
embeds an offset into that code on the basis of the first register
to be saved. */
prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
if ((sel & SAVRES_REG) == SAVRES_GPR)
sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
(regno - 13) * 4, prefix, regno);
else if ((sel & SAVRES_REG) == SAVRES_FPR)
sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
(regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
else if ((sel & SAVRES_REG) == SAVRES_VR)
sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
(regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
else
abort ();
}
else
sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
return savres_routine_name;
}
/* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
We are saving/restoring GPRs if GPR is true. */
static rtx
rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
{
int regno = ((sel & SAVRES_REG) == SAVRES_GPR
? info->first_gp_reg_save
: (sel & SAVRES_REG) == SAVRES_FPR
? info->first_fp_reg_save - 32
: (sel & SAVRES_REG) == SAVRES_VR
? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
: -1);
rtx sym;
int select = sel;
/* Don't generate bogus routine names. */
gcc_assert (FIRST_SAVRES_REGISTER <= regno
&& regno <= LAST_SAVRES_REGISTER
&& select >= 0 && select <= 12);
sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
if (sym == NULL)
{
char *name;
name = rs6000_savres_routine_name (regno, sel);
sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
= gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
}
return sym;
}
/* Emit a sequence of insns, including a stack tie if needed, for
resetting the stack pointer. If UPDT_REGNO is not 1, then don't
reset the stack pointer, but move the base of the frame into
reg UPDT_REGNO for use by out-of-line register restore routines. */
static rtx
rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
unsigned updt_regno)
{
/* If there is nothing to do, don't do anything. */
if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
return NULL_RTX;
rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
/* This blockage is needed so that sched doesn't decide to move
the sp change before the register restores. */
if (DEFAULT_ABI == ABI_V4)
return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
GEN_INT (frame_off)));
/* If we are restoring registers out-of-line, we will be using the
"exit" variants of the restore routines, which will reset the
stack for us. But we do need to point updt_reg into the
right place for those routines. */
if (frame_off != 0)
return emit_insn (gen_add3_insn (updt_reg_rtx,
frame_reg_rtx, GEN_INT (frame_off)));
else
return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
return NULL_RTX;
}
/* Return the register number used as a pointer by out-of-line
save/restore functions. */
static inline unsigned
ptr_regno_for_savres (int sel)
{
if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
}
/* Construct a parallel rtx describing the effect of a call to an
out-of-line register save/restore routine, and emit the insn
or jump_insn as appropriate. */
static rtx_insn *
rs6000_emit_savres_rtx (rs6000_stack_t *info,
rtx frame_reg_rtx, int save_area_offset, int lr_offset,
machine_mode reg_mode, int sel)
{
int i;
int offset, start_reg, end_reg, n_regs, use_reg;
int reg_size = GET_MODE_SIZE (reg_mode);
rtx sym;
rtvec p;
rtx par;
rtx_insn *insn;
offset = 0;
start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
? info->first_gp_reg_save
: (sel & SAVRES_REG) == SAVRES_FPR
? info->first_fp_reg_save
: (sel & SAVRES_REG) == SAVRES_VR
? info->first_altivec_reg_save
: -1);
end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
? 32
: (sel & SAVRES_REG) == SAVRES_FPR
? 64
: (sel & SAVRES_REG) == SAVRES_VR
? LAST_ALTIVEC_REGNO + 1
: -1);
n_regs = end_reg - start_reg;
p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
+ ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
+ n_regs);
if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
RTVEC_ELT (p, offset++) = ret_rtx;
RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
sym = rs6000_savres_routine_sym (info, sel);
RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
use_reg = ptr_regno_for_savres (sel);
if ((sel & SAVRES_REG) == SAVRES_VR)
{
/* Vector regs are saved/restored using [reg+reg] addressing. */
RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, use_reg);
RTVEC_ELT (p, offset++)
= gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
}
else
RTVEC_ELT (p, offset++)
= gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
for (i = 0; i < end_reg - start_reg; i++)
RTVEC_ELT (p, i + offset)
= gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
frame_reg_rtx, save_area_offset + reg_size * i,
(sel & SAVRES_SAVE) != 0);
if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
RTVEC_ELT (p, i + offset)
= gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
par = gen_rtx_PARALLEL (VOIDmode, p);
if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
{
insn = emit_jump_insn (par);
JUMP_LABEL (insn) = ret_rtx;
}
else
insn = emit_insn (par);
return insn;
}
/* Emit prologue code to store CR fields that need to be saved into REG. This
function should only be called when moving the non-volatile CRs to REG, it
is not a general purpose routine to move the entire set of CRs to REG.
Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
volatile CRs. */
static void
rs6000_emit_prologue_move_from_cr (rtx reg)
{
/* Only the ELFv2 ABI allows storing only selected fields. */
if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
{
int i, cr_reg[8], count = 0;
/* Collect CR fields that must be saved. */
for (i = 0; i < 8; i++)
if (save_reg_p (CR0_REGNO + i))
cr_reg[count++] = i;
/* If it's just a single one, use mfcrf. */
if (count == 1)
{
rtvec p = rtvec_alloc (1);
rtvec r = rtvec_alloc (2);
RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
RTVEC_ELT (p, 0)
= gen_rtx_SET (reg,
gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
return;
}
/* ??? It might be better to handle count == 2 / 3 cases here
as well, using logical operations to combine the values. */
}
emit_insn (gen_prologue_movesi_from_cr (reg));
}
/* Return whether the split-stack arg pointer (r12) is used. */
static bool
split_stack_arg_pointer_used_p (void)
{
/* If the pseudo holding the arg pointer is no longer a pseudo,
then the arg pointer is used. */
if (cfun->machine->split_stack_arg_pointer != NULL_RTX
&& (!REG_P (cfun->machine->split_stack_arg_pointer)
|| HARD_REGISTER_P (cfun->machine->split_stack_arg_pointer)))
return true;
/* Unfortunately we also need to do some code scanning, since
r12 may have been substituted for the pseudo. */
rtx_insn *insn;
basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
FOR_BB_INSNS (bb, insn)
if (NONDEBUG_INSN_P (insn))
{
/* A call destroys r12. */
if (CALL_P (insn))
return false;
df_ref use;
FOR_EACH_INSN_USE (use, insn)
{
rtx x = DF_REF_REG (use);
if (REG_P (x) && REGNO (x) == 12)
return true;
}
df_ref def;
FOR_EACH_INSN_DEF (def, insn)
{
rtx x = DF_REF_REG (def);
if (REG_P (x) && REGNO (x) == 12)
return false;
}
}
return bitmap_bit_p (DF_LR_OUT (bb), 12);
}
/* Return whether we need to emit an ELFv2 global entry point prologue. */
bool
rs6000_global_entry_point_prologue_needed_p (void)
{
/* Only needed for the ELFv2 ABI. */
if (DEFAULT_ABI != ABI_ELFv2)
return false;
/* With -msingle-pic-base, we assume the whole program shares the same
TOC, so no global entry point prologues are needed anywhere. */
if (TARGET_SINGLE_PIC_BASE)
return false;
/* PC-relative functions never generate a global entry point prologue. */
if (rs6000_pcrel_p ())
return false;
/* Ensure we have a global entry point for thunks. ??? We could
avoid that if the target routine doesn't need a global entry point,
but we do not know whether this is the case at this point. */
if (cfun->is_thunk)
return true;
/* For regular functions, rs6000_emit_prologue sets this flag if the
routine ever uses the TOC pointer. */
return cfun->machine->r2_setup_needed;
}
/* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
sbitmap
rs6000_get_separate_components (void)
{
rs6000_stack_t *info = rs6000_stack_info ();
if (WORLD_SAVE_P (info))
return NULL;
gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
&& !(info->savres_strategy & REST_MULTIPLE));
/* Component 0 is the save/restore of LR (done via GPR0).
Component 2 is the save of the TOC (GPR2).
Components 13..31 are the save/restore of GPR13..GPR31.
Components 46..63 are the save/restore of FPR14..FPR31. */
cfun->machine->n_components = 64;
sbitmap components = sbitmap_alloc (cfun->machine->n_components);
bitmap_clear (components);
int reg_size = TARGET_32BIT ? 4 : 8;
int fp_reg_size = 8;
/* The GPRs we need saved to the frame. */
if ((info->savres_strategy & SAVE_INLINE_GPRS)
&& (info->savres_strategy & REST_INLINE_GPRS))
{
int offset = info->gp_save_offset;
if (info->push_p)
offset += info->total_size;
for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
{
if (IN_RANGE (offset, -0x8000, 0x7fff)
&& save_reg_p (regno))
bitmap_set_bit (components, regno);
offset += reg_size;
}
}
/* Don't mess with the hard frame pointer. */
if (frame_pointer_needed)
bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
/* Don't mess with the fixed TOC register. */
if ((TARGET_TOC && TARGET_MINIMAL_TOC)
|| (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
|| (flag_pic && DEFAULT_ABI == ABI_DARWIN))
bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
/* The FPRs we need saved to the frame. */
if ((info->savres_strategy & SAVE_INLINE_FPRS)
&& (info->savres_strategy & REST_INLINE_FPRS))
{
int offset = info->fp_save_offset;
if (info->push_p)
offset += info->total_size;
for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
{
if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
bitmap_set_bit (components, regno);
offset += fp_reg_size;
}
}
/* Optimize LR save and restore if we can. This is component 0. Any
out-of-line register save/restore routines need LR. */
if (info->lr_save_p
&& !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
&& (info->savres_strategy & SAVE_INLINE_GPRS)
&& (info->savres_strategy & REST_INLINE_GPRS)
&& (info->savres_strategy & SAVE_INLINE_FPRS)
&& (info->savres_strategy & REST_INLINE_FPRS)
&& (info->savres_strategy & SAVE_INLINE_VRS)
&& (info->savres_strategy & REST_INLINE_VRS))
{
int offset = info->lr_save_offset;
if (info->push_p)
offset += info->total_size;
if (IN_RANGE (offset, -0x8000, 0x7fff))
bitmap_set_bit (components, 0);
}
/* Optimize saving the TOC. This is component 2. */
if (cfun->machine->save_toc_in_prologue)
bitmap_set_bit (components, 2);
return components;
}
/* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
sbitmap
rs6000_components_for_bb (basic_block bb)
{
rs6000_stack_t *info = rs6000_stack_info ();
bitmap in = DF_LIVE_IN (bb);
bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
sbitmap components = sbitmap_alloc (cfun->machine->n_components);
bitmap_clear (components);
/* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
/* GPRs. */
for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
if (bitmap_bit_p (in, regno)
|| bitmap_bit_p (gen, regno)
|| bitmap_bit_p (kill, regno))
bitmap_set_bit (components, regno);
/* FPRs. */
for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
if (bitmap_bit_p (in, regno)
|| bitmap_bit_p (gen, regno)
|| bitmap_bit_p (kill, regno))
bitmap_set_bit (components, regno);
/* The link register. */
if (bitmap_bit_p (in, LR_REGNO)
|| bitmap_bit_p (gen, LR_REGNO)
|| bitmap_bit_p (kill, LR_REGNO))
bitmap_set_bit (components, 0);
/* The TOC save. */
if (bitmap_bit_p (in, TOC_REGNUM)
|| bitmap_bit_p (gen, TOC_REGNUM)
|| bitmap_bit_p (kill, TOC_REGNUM))
bitmap_set_bit (components, 2);
return components;
}
/* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
void
rs6000_disqualify_components (sbitmap components, edge e,
sbitmap edge_components, bool /*is_prologue*/)
{
/* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
live where we want to place that code. */
if (bitmap_bit_p (edge_components, 0)
&& bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
{
if (dump_file)
fprintf (dump_file, "Disqualifying LR because GPR0 is live "
"on entry to bb %d\n", e->dest->index);
bitmap_clear_bit (components, 0);
}
}
/* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
void
rs6000_emit_prologue_components (sbitmap components)
{
rs6000_stack_t *info = rs6000_stack_info ();
rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed_indeed
? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM);
machine_mode reg_mode = Pmode;
int reg_size = TARGET_32BIT ? 4 : 8;
machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
int fp_reg_size = 8;
/* Prologue for LR. */
if (bitmap_bit_p (components, 0))
{
rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
rtx reg = gen_rtx_REG (reg_mode, 0);
rtx_insn *insn = emit_move_insn (reg, lr);
RTX_FRAME_RELATED_P (insn) = 1;
add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr));
int offset = info->lr_save_offset;
if (info->push_p)
offset += info->total_size;
insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
RTX_FRAME_RELATED_P (insn) = 1;
rtx mem = copy_rtx (SET_DEST (single_set (insn)));
add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
}
/* Prologue for TOC. */
if (bitmap_bit_p (components, 2))
{
rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
}
/* Prologue for the GPRs. */
int offset = info->gp_save_offset;
if (info->push_p)
offset += info->total_size;
for (int i = info->first_gp_reg_save; i < 32; i++)
{
if (bitmap_bit_p (components, i))
{
rtx reg = gen_rtx_REG (reg_mode, i);
rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
RTX_FRAME_RELATED_P (insn) = 1;
rtx set = copy_rtx (single_set (insn));
add_reg_note (insn, REG_CFA_OFFSET, set);
}
offset += reg_size;
}
/* Prologue for the FPRs. */
offset = info->fp_save_offset;
if (info->push_p)
offset += info->total_size;
for (int i = info->first_fp_reg_save; i < 64; i++)
{
if (bitmap_bit_p (components, i))
{
rtx reg = gen_rtx_REG (fp_reg_mode, i);
rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
RTX_FRAME_RELATED_P (insn) = 1;
rtx set = copy_rtx (single_set (insn));
add_reg_note (insn, REG_CFA_OFFSET, set);
}
offset += fp_reg_size;
}
}
/* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
void
rs6000_emit_epilogue_components (sbitmap components)
{
rs6000_stack_t *info = rs6000_stack_info ();
rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed_indeed
? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM);
machine_mode reg_mode = Pmode;
int reg_size = TARGET_32BIT ? 4 : 8;
machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
int fp_reg_size = 8;
/* Epilogue for the FPRs. */
int offset = info->fp_save_offset;
if (info->push_p)
offset += info->total_size;
for (int i = info->first_fp_reg_save; i < 64; i++)
{
if (bitmap_bit_p (components, i))
{
rtx reg = gen_rtx_REG (fp_reg_mode, i);
rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
RTX_FRAME_RELATED_P (insn) = 1;
add_reg_note (insn, REG_CFA_RESTORE, reg);
}
offset += fp_reg_size;
}
/* Epilogue for the GPRs. */
offset = info->gp_save_offset;
if (info->push_p)
offset += info->total_size;
for (int i = info->first_gp_reg_save; i < 32; i++)
{
if (bitmap_bit_p (components, i))
{
rtx reg = gen_rtx_REG (reg_mode, i);
rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
RTX_FRAME_RELATED_P (insn) = 1;
add_reg_note (insn, REG_CFA_RESTORE, reg);
}
offset += reg_size;
}
/* Epilogue for LR. */
if (bitmap_bit_p (components, 0))
{
int offset = info->lr_save_offset;
if (info->push_p)
offset += info->total_size;
rtx reg = gen_rtx_REG (reg_mode, 0);
rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
insn = emit_move_insn (lr, reg);
RTX_FRAME_RELATED_P (insn) = 1;
add_reg_note (insn, REG_CFA_RESTORE, lr);
}
}
/* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
void
rs6000_set_handled_components (sbitmap components)
{
rs6000_stack_t *info = rs6000_stack_info ();
for (int i = info->first_gp_reg_save; i < 32; i++)
if (bitmap_bit_p (components, i))
cfun->machine->gpr_is_wrapped_separately[i] = true;
for (int i = info->first_fp_reg_save; i < 64; i++)
if (bitmap_bit_p (components, i))
cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
if (bitmap_bit_p (components, 0))
cfun->machine->lr_is_wrapped_separately = true;
if (bitmap_bit_p (components, 2))
cfun->machine->toc_is_wrapped_separately = true;
}
/* VRSAVE is a bit vector representing which AltiVec registers
are used. The OS uses this to determine which vector
registers to save on a context switch. We need to save
VRSAVE on the stack frame, add whatever AltiVec registers we
used in this function, and do the corresponding magic in the
epilogue. */
static void
emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
{
/* Get VRSAVE into a GPR. */
rtx reg = gen_rtx_REG (SImode, save_regno);
rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
if (TARGET_MACHO)
emit_insn (gen_get_vrsave_internal (reg));
else
emit_insn (gen_rtx_SET (reg, vrsave));
/* Save VRSAVE. */
int offset = info->vrsave_save_offset + frame_off;
emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
/* Include the registers in the mask. */
emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
emit_insn (generate_set_vrsave (reg, info, 0));
}
/* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
called, it left the arg pointer to the old stack in r29. Otherwise, the
arg pointer is the top of the current frame. */
static void
emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
{
cfun->machine->split_stack_argp_used = true;
if (sp_adjust)
{
rtx r12 = gen_rtx_REG (Pmode, 12);
rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
emit_insn_before (set_r12, sp_adjust);
}
else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
{
rtx r12 = gen_rtx_REG (Pmode, 12);
if (frame_off == 0)
emit_move_insn (r12, frame_reg_rtx);
else
emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
}
if (info->push_p)
{
rtx r12 = gen_rtx_REG (Pmode, 12);
rtx r29 = gen_rtx_REG (Pmode, 29);
rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
rtx not_more = gen_label_rtx ();
rtx jump;
jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
gen_rtx_LABEL_REF (VOIDmode, not_more),
pc_rtx);
jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
JUMP_LABEL (jump) = not_more;
LABEL_NUSES (not_more) += 1;
emit_move_insn (r12, r29);
emit_label (not_more);
}
}
/* Emit function prologue as insns. */
void
rs6000_emit_prologue (void)
{
rs6000_stack_t *info = rs6000_stack_info ();
machine_mode reg_mode = Pmode;
int reg_size = TARGET_32BIT ? 4 : 8;
machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
int fp_reg_size = 8;
rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
rtx frame_reg_rtx = sp_reg_rtx;
unsigned int cr_save_regno;
rtx cr_save_rtx = NULL_RTX;
rtx_insn *insn;
int strategy;
int using_static_chain_p
= (cfun->static_chain_decl != NULL_TREE
&& df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
&& call_used_or_fixed_reg_p (STATIC_CHAIN_REGNUM));
int using_split_stack = (flag_split_stack
&& (lookup_attribute ("no_split_stack",
DECL_ATTRIBUTES (cfun->decl))
== NULL));
frame_pointer_needed_indeed
= frame_pointer_needed && df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM);
/* Offset to top of frame for frame_reg and sp respectively. */
HOST_WIDE_INT frame_off = 0;
HOST_WIDE_INT sp_off = 0;
/* sp_adjust is the stack adjusting instruction, tracked so that the
insn setting up the split-stack arg pointer can be emitted just
prior to it, when r12 is not used here for other purposes. */
rtx_insn *sp_adjust = 0;
#if CHECKING_P
/* Track and check usage of r0, r11, r12. */
int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
#define START_USE(R) do \
{ \
gcc_assert ((reg_inuse & (1 << (R))) == 0); \
reg_inuse |= 1 << (R); \
} while (0)
#define END_USE(R) do \
{ \
gcc_assert ((reg_inuse & (1 << (R))) != 0); \
reg_inuse &= ~(1 << (R)); \
} while (0)
#define NOT_INUSE(R) do \
{ \
gcc_assert ((reg_inuse & (1 << (R))) == 0); \
} while (0)
#else
#define START_USE(R) do {} while (0)
#define END_USE(R) do {} while (0)
#define NOT_INUSE(R) do {} while (0)
#endif
if (DEFAULT_ABI == ABI_ELFv2
&& !TARGET_SINGLE_PIC_BASE)
{
cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
/* With -mminimal-toc we may generate an extra use of r2 below. */
if (TARGET_TOC && TARGET_MINIMAL_TOC
&& !constant_pool_empty_p ())
cfun->machine->r2_setup_needed = true;
}
if (flag_stack_usage_info)
current_function_static_stack_size = info->total_size;
if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
{
HOST_WIDE_INT size = info->total_size;
if (crtl->is_leaf && !cfun->calls_alloca)
{
if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
rs6000_emit_probe_stack_range (get_stack_check_protect (),
size - get_stack_check_protect ());
}
else if (size > 0)
rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
}
if (TARGET_FIX_AND_CONTINUE)
{
/* gdb on darwin arranges to forward a function from the old
address by modifying the first 5 instructions of the function
to branch to the overriding function. This is necessary to
permit function pointers that point to the old function to
actually forward to the new function. */
emit_insn (gen_nop ());
emit_insn (gen_nop ());
emit_insn (gen_nop ());
emit_insn (gen_nop ());
emit_insn (gen_nop ());
}
/* Handle world saves specially here. */
if (WORLD_SAVE_P (info))
{
int i, j, sz;
rtx treg;
rtvec p;
rtx reg0;
/* save_world expects lr in r0. */
reg0 = gen_rtx_REG (Pmode, 0);
if (info->lr_save_p)
{
insn = emit_move_insn (reg0,
gen_rtx_REG (Pmode, LR_REGNO));
RTX_FRAME_RELATED_P (insn) = 1;
}
/* The SAVE_WORLD and RESTORE_WORLD routines make a number of
assumptions about the offsets of various bits of the stack
frame. */
gcc_assert (info->gp_save_offset == -220
&& info->fp_save_offset == -144
&& info->lr_save_offset == 8
&& info->cr_save_offset == 4
&& info->push_p
&& info->lr_save_p
&& (!crtl->calls_eh_return
|| info->ehrd_offset == -432)
&& info->vrsave_save_offset == -224
&& info->altivec_save_offset == -416);
treg = gen_rtx_REG (SImode, 11);
emit_move_insn (treg, GEN_INT (-info->total_size));
/* SAVE_WORLD takes the caller's LR in R0 and the frame size
in R11. It also clobbers R12, so beware! */
/* Preserve CR2 for save_world prologues */
sz = 5;
sz += 32 - info->first_gp_reg_save;
sz += 64 - info->first_fp_reg_save;
sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
p = rtvec_alloc (sz);
j = 0;
RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, LR_REGNO);
RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
gen_rtx_SYMBOL_REF (Pmode,
"*save_world"));
/* We do floats first so that the instruction pattern matches
properly. */
for (i = 0; i < 64 - info->first_fp_reg_save; i++)
RTVEC_ELT (p, j++)