| commit | acbb5ef06ee97849ecd5412ab56c1dff0f0d2fcf | [log] [tgz] |
|---|---|---|
| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | Tue Oct 11 15:50:11 2022 +0200 |
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | Fri Nov 18 21:15:24 2022 +0100 |
| tree | 58f171c628c42a4bea78af23ae988faabe0bf90b | |
| parent | 23d9f62c50d935462ecda5516746037a474c25cd [diff] |
RISC-V: Optimize branches testing a bit-range or a shifted immediate gcc/ChangeLog: * config/riscv/predicates.md (shifted_const_arith_operand): New predicate. (uimm_extra_bit_operand): New predicate. * config/riscv/riscv.md (*branch<ANYI:mode>_shiftedarith_equals_zero): New pattern. (*branch<ANYI:mode>_shiftedmask_equals_zero): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/branch-1.c: New test.