tree 58f171c628c42a4bea78af23ae988faabe0bf90b
parent 23d9f62c50d935462ecda5516746037a474c25cd
author Philipp Tomsich <philipp.tomsich@vrull.eu> 1665496211 +0200
committer Philipp Tomsich <philipp.tomsich@vrull.eu> 1668802524 +0100

RISC-V: Optimize branches testing a bit-range or a shifted immediate

gcc/ChangeLog:

	* config/riscv/predicates.md (shifted_const_arith_operand): New predicate.
	(uimm_extra_bit_operand): New predicate.
	* config/riscv/riscv.md (*branch<ANYI:mode>_shiftedarith_equals_zero):
	New pattern.
	(*branch<ANYI:mode>_shiftedmask_equals_zero): New pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/branch-1.c: New test.