)]}'
{
  "commit": "b8c702f508a8111c68ee00a4ff1a00a64f6e25fc",
  "tree": "e38ae09b20a0c248a55c7f684498b74468e3332f",
  "parents": [
    "f0767ec84b4381fb22b6226acb76bbd9bbd18d6f"
  ],
  "author": {
    "name": "Kyrylo Tkachov",
    "email": "ktkachov@nvidia.com",
    "time": "Tue Sep 02 00:43:14 2025 -0700"
  },
  "committer": {
    "name": "Kyrylo Tkachov",
    "email": "ktkachov@nvidia.com",
    "time": "Mon Sep 15 16:13:14 2025 +0200"
  },
  "message": "aarch64: PR target/121749: Use correct predicate for narrowing shift amounts\n\nWith g:d20b2ad845876eec0ee80a3933ad49f9f6c4ee30 the narrowing shift instructions\nare now represented with standard RTL and more merging optimisations occur.\nThis exposed a wrong predicate for the shift amount operand.\nThe shift amount is the number of bits of the narrow destination, not the input\nsources.\nCorrect this by using the vn_mode attribute when specifying the predicate, which\nexists for this purpose.\n\nI\u0027ve spotted a few more narrowing shift patterns that need the restriction, so\nthey are updated as well.\n\nBootstrapped and tested on aarch64-none-linux-gnu.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n\ngcc/\n\n\tPR target/121749\n\t* config/aarch64/aarch64-simd.md (aarch64_\u003cshrn_op\u003eshrn_n\u003cmode\u003e):\n\tUse aarch64_simd_shift_imm_offset_\u003cvn_mode\u003e instead of\n\taarch64_simd_shift_imm_offset_\u003cve_mode\u003e predicate.\n\t(aarch64_\u003cshrn_op\u003eshrn_n\u003cmode\u003e VQN define_expand): Likewise.\n\t(*aarch64_\u003cshrn_op\u003ershrn_n\u003cmode\u003e_insn): Likewise.\n\t(aarch64_\u003cshrn_op\u003ershrn_n\u003cmode\u003e): Likewise.\n\t(aarch64_\u003cshrn_op\u003ershrn_n\u003cmode\u003e VQN define_expand): Likewise.\n\t(aarch64_sqshrun_n\u003cmode\u003e_insn): Likewise.\n\t(aarch64_sqshrun_n\u003cmode\u003e): Likewise.\n\t(aarch64_sqshrun_n\u003cmode\u003e VQN define_expand): Likewise.\n\t(aarch64_sqrshrun_n\u003cmode\u003e_insn): Likewise.\n\t(aarch64_sqrshrun_n\u003cmode\u003e): Likewise.\n\t(aarch64_sqrshrun_n\u003cmode\u003e): Likewise.\n\t* config/aarch64/iterators.md (vn_mode): Handle DI, SI, HI modes.\n\ngcc/testsuite/\n\n\tPR target/121749\n\t* gcc.target/aarch64/simd/pr121749.c: New test.\n\n(cherry picked from commit cb508e54140687a50790059fac548d87515df6be)\n",
  "tree_diff": [
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      "old_mode": 33188,
      "old_path": "gcc/config/aarch64/aarch64-simd.md",
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      "new_mode": 33188,
      "new_path": "gcc/config/aarch64/aarch64-simd.md"
    },
    {
      "type": "modify",
      "old_id": "47a9bdf2d038b7e7d0211a5c4ed9d3b3e3b1fa5e",
      "old_mode": 33188,
      "old_path": "gcc/config/aarch64/iterators.md",
      "new_id": "4d60322b45ddb310a83375c2817a8a95b6c7d4b4",
      "new_mode": 33188,
      "new_path": "gcc/config/aarch64/iterators.md"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c4e1a2d76cfb3e8fee6c0a23a2e77b592782a87d",
      "new_mode": 33188,
      "new_path": "gcc/testsuite/gcc.target/aarch64/simd/pr121749.c"
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}