)]}'
{
  "commit": "c69c5e7b8e08b99701054c19ae26730979ebb78f",
  "tree": "2aacefc43bc352af38e1bcb7696148d9a9b85211",
  "parents": [
    "d7a18fca936d64d8c6e7ef7c535e2cfc6665aa8d"
  ],
  "author": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Thu Aug 27 08:36:28 2026 +0800"
  },
  "committer": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Fri Aug 28 08:45:34 2026 +0800"
  },
  "message": "RISC-V: Allow RVV register overlap for vwmacc[u].vx\n\nLike vwmacc[u].vv, allow the rvv register overlap for the dual\nwiden ternary vx insn vwmacc.vx and vwmaccu.vx.\n\ngcc/ChangeLog:\n\n\t* config/riscv/vector.md: Leverage Wvr constraint.\n\nSigned-off-by: Pan Li \u003cpan2.li@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ad537557cd4c34557083a9edec5fcce703c6779b",
      "old_mode": 33188,
      "old_path": "gcc/config/riscv/vector.md",
      "new_id": "b1036b930bb978f09587f77a68ed21f6338e16c2",
      "new_mode": 33188,
      "new_path": "gcc/config/riscv/vector.md"
    }
  ]
}