/* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu.
   Copyright (C) 2002-2021 Free Software Foundation, Inc.
   Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
		on behalf of Synopsys Inc.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3.  If not see
<http://www.gnu.org/licenses/>.  */

/* Some insns set all condition code flags, some only set the ZNC flags, and
   some only set the ZN flags.  */

CC_MODE (CC_ZN);
CC_MODE (CC_Z);
CC_MODE (CC_C);
CC_MODE (CC_FP_GT);
CC_MODE (CC_FP_GE);
CC_MODE (CC_FP_ORD);
CC_MODE (CC_FP_UNEQ);
CC_MODE (CC_FPX);

/* Vector modes.  */
VECTOR_MODES (INT, 4);        /*            V4QI V2HI */
VECTOR_MODES (INT, 8);        /*       V8QI V4HI V2SI */
VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI */

/* FPU condition flags.  */
CC_MODE (CC_FPU);
CC_MODE (CC_FPUE);
CC_MODE (CC_FPU_UNEQ);