; Options for the RISC-V port of the compiler
;
; Copyright (C) 2011-2022 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; <http://www.gnu.org/licenses/>.

HeaderInclude
config/riscv/riscv-opts.h

mbig-endian
Target RejectNegative Mask(BIG_ENDIAN)
Assume target CPU is configured as big endian.

mlittle-endian
Target RejectNegative InverseMask(BIG_ENDIAN)
Assume target CPU is configured as little endian.

mbranch-cost=
Target RejectNegative Joined UInteger Var(riscv_branch_cost)
-mbranch-cost=N	Set the cost of branches to roughly N instructions.

mplt
Target Var(TARGET_PLT) Init(1)
When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.

mabi=
Target RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32) Negative(mabi=)
Specify integer and floating-point calling convention.

mpreferred-stack-boundary=
Target RejectNegative Joined UInteger Var(riscv_preferred_stack_boundary_arg)
Attempt to keep stack aligned to this power of 2.

Enum
Name(abi_type) Type(enum riscv_abi_type)
Supported ABIs (for use with the -mabi= option):

EnumValue
Enum(abi_type) String(ilp32) Value(ABI_ILP32)

EnumValue
Enum(abi_type) String(ilp32e) Value(ABI_ILP32E)

EnumValue
Enum(abi_type) String(ilp32f) Value(ABI_ILP32F)

EnumValue
Enum(abi_type) String(ilp32d) Value(ABI_ILP32D)

EnumValue
Enum(abi_type) String(lp64) Value(ABI_LP64)

EnumValue
Enum(abi_type) String(lp64f) Value(ABI_LP64F)

EnumValue
Enum(abi_type) String(lp64d) Value(ABI_LP64D)

mfdiv
Target Mask(FDIV)
Use hardware floating-point divide and square root instructions.

mdiv
Target Mask(DIV)
Use hardware instructions for integer division.

march=
Target RejectNegative Joined Negative(march=)
-march=	Generate code for given RISC-V ISA (e.g. RV64IM).  ISA strings must be
lower-case.

mtune=
Target RejectNegative Joined Var(riscv_tune_string)
-mtune=PROCESSOR	Optimize the output for PROCESSOR.

mcpu=
Target RejectNegative Joined Var(riscv_cpu_string)
-mcpu=PROCESSOR	Use architecture of and optimize the output for PROCESSOR.

msmall-data-limit=
Target Joined UInteger Var(g_switch_value) Init(8)
-msmall-data-limit=N	Put global and static data smaller than <number> bytes into a special section (on some targets).

msave-restore
Target Mask(SAVE_RESTORE)
Use smaller but slower prologue and epilogue code.

mshorten-memrefs
Target Bool Var(riscv_mshorten_memrefs) Init(1)
Convert BASE + LARGE_OFFSET addresses to NEW_BASE + SMALL_OFFSET to allow more
memory accesses to be generated as compressed instructions.  Currently targets
32-bit integer load/stores.

mcmodel=
Target RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL)
Specify the code model.

mstrict-align
Target Mask(STRICT_ALIGN) Save
Do not generate unaligned memory accesses.

Enum
Name(code_model) Type(enum riscv_code_model)
Known code models (for use with the -mcmodel= option):

EnumValue
Enum(code_model) String(medlow) Value(CM_MEDLOW)

EnumValue
Enum(code_model) String(medany) Value(CM_MEDANY)

mexplicit-relocs
Target Mask(EXPLICIT_RELOCS)
Use %reloc() operators, rather than assembly macros, to load addresses.

mrelax
Target Bool Var(riscv_mrelax) Init(1)
Take advantage of linker relaxations to reduce the number of instructions
required to materialize symbol addresses.

mcsr-check
Target Bool Var(riscv_mcsr_check) Init(0)
Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
The ISA-dependent CSR are only valid when the specific ISA is set.  The
read-only CSR can not be written by the CSR instructions.

Mask(64BIT)

Mask(MUL)

Mask(ATOMIC)

Mask(HARD_FLOAT)

Mask(DOUBLE_FLOAT)

Mask(RVC)

Mask(RVE)

Mask(VECTOR)

mriscv-attribute
Target Var(riscv_emit_attribute_p) Init(-1)
Emit RISC-V ELF attribute.

malign-data=
Target RejectNegative Joined Var(riscv_align_data_type) Enum(riscv_align_data) Init(riscv_align_data_type_xlen)
Use the given data alignment.

Enum
Name(riscv_align_data) Type(enum riscv_align_data)
Known data alignment choices (for use with the -malign-data= option):

EnumValue
Enum(riscv_align_data) String(xlen) Value(riscv_align_data_type_xlen)

EnumValue
Enum(riscv_align_data) String(natural) Value(riscv_align_data_type_natural)

mstack-protector-guard=
Target RejectNegative Joined Enum(stack_protector_guard) Var(riscv_stack_protector_guard) Init(SSP_GLOBAL)
Use given stack-protector guard.

Enum
Name(stack_protector_guard) Type(enum stack_protector_guard)
Valid arguments to -mstack-protector-guard=:

EnumValue
Enum(stack_protector_guard) String(tls) Value(SSP_TLS)

EnumValue
Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)

mstack-protector-guard-reg=
Target RejectNegative Joined Var(riscv_stack_protector_guard_reg_str)
Use the given base register for addressing the stack-protector guard.

TargetVariable
int riscv_stack_protector_guard_reg = 0

mstack-protector-guard-offset=
Target RejectNegative Joined Integer Var(riscv_stack_protector_guard_offset_str)
Use the given offset for addressing the stack-protector guard.

TargetVariable
long riscv_stack_protector_guard_offset = 0

TargetVariable
int riscv_zi_subext

TargetVariable
int riscv_za_subext

TargetVariable
int riscv_zb_subext

TargetVariable
int riscv_zinx_subext

TargetVariable
int riscv_zk_subext

TargetVariable
int riscv_vector_elen_flags

TargetVariable
int riscv_zvl_flags

TargetVariable
int riscv_zicmo_subext

TargetVariable
int riscv_zf_subext

TargetVariable
int riscv_zm_subext

TargetVariable
int riscv_sv_subext

Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):

EnumValue
Enum(isa_spec_class) String(2.2) Value(ISA_SPEC_CLASS_2P2)

EnumValue
Enum(isa_spec_class) String(20190608) Value(ISA_SPEC_CLASS_20190608)

EnumValue
Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213)

misa-spec=
Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC)
Set the version of RISC-V ISA spec.