)]}'
{
  "commit": "e7efddbd351e00fc5cda58dd063947784bf7e8b3",
  "tree": "3ae009705d87cf6c673dcb6fd308a9661d7d3969",
  "parents": [
    "a1fc8045881850df83c5143ea6d9311ce3a0c540"
  ],
  "author": {
    "name": "Xi Ruoyao",
    "email": "xry111@xry111.site",
    "time": "Tue Jun 23 22:07:34 2026 +0800"
  },
  "committer": {
    "name": "Xi Ruoyao",
    "email": "xry111@xry111.site",
    "time": "Thu Jun 25 16:43:50 2026 +0800"
  },
  "message": "mips: fix unintialized operand use in sync_{old,new}_\u003coptab\u003e_12 [PR 125628]\n\nIn GCC, if the RTL template of define_insn has multiple elements, it\u0027s\ntreated as a parallel expression.  And, \"in parallel\" means that first\nall the values used in the invidiviual side-effects are computed, and\nsecond all the actual side-effects are performed.  So when the value of\noperand 1 (the output reg) is used, it\u0027s not set yet.\n\nWhen optimization is enabled, the uninitialized value is replaced with 0\nand then for e.g. if atomic_hiqi_op is plus, (plus (0) (val)) is folded\nto simply (val).  Now the RTL template happens to be matched by\nsync_old_nand_12 (of which the RTL is written in a really inconsistent\nway), causing \"0 + 1 \u003d -1\".\n\nSo fix the uninitialized operand use, i.e. (match_dup 0) should be\n(match_dup 1).  Also slightly alter the source of the set for the memory\nin sync_new_\u003coptab\u003e_12 to make it clear the value in the reg and in the\nmemory should be same after the operation.\n\ngcc/\n\n\tPR target/125628\n\t* config/mips/sync.md (sync_old_\u003coptab\u003e\u003cmode\u003e): Fix\n\tuninitialized operand use.\n\t(sync_new_\u003coptab\u003e\u003cmode\u003e): Fix uninitialized operand use, use the\n\tsame expression for the set source of operand 0 and 1.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1d0a977066b8e5c33e0ea694c15b1bd7bb6cbef3",
      "old_mode": 33188,
      "old_path": "gcc/config/mips/sync.md",
      "new_id": "beabb7fe555e25dd5b499270e9d6c6f47c59c795",
      "new_mode": 33188,
      "new_path": "gcc/config/mips/sync.md"
    }
  ]
}