)]}'
{
  "commit": "eca9778fc8cabd032bbb68de3765aa45dabbc3e4",
  "tree": "b46bbea43d8e0bcd21d67236c64797a8a3732451",
  "parents": [
    "9e8af6864b9fdfae109248a4d162bba9cc008b60"
  ],
  "author": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Mon Jul 21 15:41:00 2025 +0100"
  },
  "committer": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Mon Jul 21 15:41:00 2025 +0100"
  },
  "message": "aarch64: Fix neon-sve-bridge.c failures for big-endian\n\nLowpart subregs are generally disallowed on big-endian SVE vector\nregisters, since the first memory element is stored at the least\nsignificant end of the register, rather than the most significant end.\n(See the comment at the head of aarch64-sve.md for details,\nand aarch64_modes_compatible_p for the implementation.)\n\nThis means that arm_sve_neon_bridge.h needs to use custom define_insns\nfor big-endian targets, in lieu of using lowpart subregs.  However,\none of those define_insns relied on the prohibited lowparts internally,\nto convert an Advanced SIMD register to an SVE register.  Since the\nlowpart is not allowed, the lowpart_subreg would return null, leading\nto a later ICE.\n\nThe simplest fix seems to be to use %Z instead, to force the Advanced\nSIMD register to be written as an SVE register.\n\ngcc/\n\t* config/aarch64/aarch64-sve.md (@aarch64_sve_set_neonq_\u003cmode\u003e):\n\tUse %Z instead of lowpart_subreg.  Tweak formatting.\n\n(cherry picked from commit 69c839c7361430ec27d1f13f909531b872588f27)\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0728cccad4fbe1a10a94baa9f2709a475a5a5e7c",
      "old_mode": 33188,
      "old_path": "gcc/config/aarch64/aarch64-sve.md",
      "new_id": "f8f744c263b9e8e19d6ad3dd08cec2992c8fdabf",
      "new_mode": 33188,
      "new_path": "gcc/config/aarch64/aarch64-sve.md"
    }
  ]
}