)]}'
{
  "commit": "f043ef2b6a59088b16a269b55f09023f76c92e32",
  "tree": "f0e5e435432eabbe4b538dd5e309af42f26ce39c",
  "parents": [
    "d109ad5e96ee9d31cbab0bba385fb490275a9937"
  ],
  "author": {
    "name": "Robin Dapp",
    "email": "rdapp@ventanamicro.com",
    "time": "Tue Feb 25 12:55:08 2025 +0100"
  },
  "committer": {
    "name": "Robin Dapp",
    "email": "rdapp@ventanamicro.com",
    "time": "Thu Mar 13 10:29:44 2025 +0100"
  },
  "message": "RISC-V: Adjust LMUL when using maximum SEW [PR117955].\n\nWhen merging two vsetvls that both only demand \"SEW \u003e\u003d ...\" we\nuse their maximum SEW and keep the LMUL.  That may lead to invalid\nvector configurations like\n  e64, mf4.\nAs we make sure that the SEW requirements overlap we can use the SEW\nand LMUL of the configuration with the larger SEW.\n\nMa Jin already touched this merge rule some weeks ago and fixed the\nratio calculation (r15-6873).  Calculating the ratio from an invalid\nSEW/LMUL combination lead to an overflow in the ratio variable, though.\nI\u0027d argue the proper fix is to update SEW and LMUL, keeping the ratio\nas before.  This \"breaks\" bug-10.c but its check only checked for a\nworkaround anyway so I turned it into a run test.\n\nMa Jin helped minify the PR\u0027s test and provided a larger test case for\nbug-10.\n\n\tPR target/117955\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-vsetvl.cc: Use LMUL/ratio from vsetvl with\n\tlarger SEW.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/base/bug-10.c: Convert to run test.\n\t* gcc.target/riscv/rvv/base/bug-10-2.c: New test.\n\t* gcc.target/riscv/rvv/base/pr117955.c: New test.\n",
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