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| \begin{document} |
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| \vspace*{7cm} |
| \begin{center} |
| {\Large Intel\textsuperscript{\textregistered} Offload Runtime Library }\\ |
| \vspace*{1cm} |
| {\large Generated by Doxygen $doxygenversion }\\ |
| \vspace*{0.5cm} |
| {\small $datetime }\\ |
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| |
| {\bf FTC Optimization Notice} |
| |
| Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for |
| optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, |
| SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the |
| availability, functionality, or effectiveness of any optimization on microprocessors not |
| manufactured by Intel. |
| |
| Microprocessor-dependent optimizations in this product are intended for use with Intel |
| microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for |
| Intel microprocessors. Please refer to the applicable product User and Reference Guides for |
| more information regarding the specific instruction sets covered by this notice. |
| |
| Notice revision \#20110804 |
| |
| \vspace*{0.5cm} |
| |
| {\bf Trademarks} |
| |
| Intel, Xeon, and Intel Xeon Phi are trademarks of Intel Corporation in the U.S. and/or other countries. |
| |
| This document is Copyright \textcopyright 2014-2016, Intel Corporation. All rights reserved. |
| |
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