)]}'
{
  "commit": "f56a404195fa986d867f015f85f4f6fcbdc4c656",
  "tree": "8480c5e729b38f9d7ac302768e820c9d470ab37c",
  "parents": [
    "d57755dd2dcb3e1bf6d72bc2aeaa22a7a027a5c7"
  ],
  "author": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Sun Aug 23 20:02:43 2026 +0800"
  },
  "committer": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Tue Aug 25 11:53:22 2026 +0800"
  },
  "message": "RISC-V: Allow RVV register overlap for vwmulsu.vx\n\nLike vw{add,sub,mul}[u].vx, allow the rvv register overlap for\nthe dual widen vx insn vwmulsu.vx.\n\ngcc/ChangeLog:\n\n\t* config/riscv/vector.md: Leverage Wvr constraint.\n\nSigned-off-by: Pan Li \u003cpan2.li@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "891561bebb7052ea71129ad416224002660d9772",
      "old_mode": 33188,
      "old_path": "gcc/config/riscv/vector.md",
      "new_id": "ad537557cd4c34557083a9edec5fcce703c6779b",
      "new_mode": 33188,
      "new_path": "gcc/config/riscv/vector.md"
    }
  ]
}