)]}'
{
  "commit": "fc3efdeb72acb145a5a4772d88a2367eef535edf",
  "tree": "6e646fe6c84dd5588773e6f5dee43b15d1bde0cc",
  "parents": [
    "13fa720ce146b00199ec7a8c5854efd6b0c1f101"
  ],
  "author": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Thu Jul 16 12:57:02 2026 +0800"
  },
  "committer": {
    "name": "Pan Li",
    "email": "pan2.li@intel.com",
    "time": "Sat Jul 18 19:50:39 2026 +0800"
  },
  "message": "RISC-V: Add test cases for vfcvt.x.f.v reg overlap\n\nAdd test cases for vfwcvt.x.f.v register group overlap, please\nnote it is not overlap as much as possible.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_x-f16-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_x-f16-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_x-f16-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_x-f16-mf2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_x-f16-mf4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_x-f32-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_x-f32-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_x-f32-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_x-f32-mf2.c: New test.\n\nSigned-off-by: Pan Li \u003cpan2.li@intel.com\u003e\n",
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