)]}'
{
  "commit": "ffd580462aa6fc2a86fa4961296ef240b60e1864",
  "tree": "0a3a01e9ebd33bbac81de30ff64950831be9159f",
  "parents": [
    "8596c662854b8693e1e9f075b6ccee83bdcf30d7"
  ],
  "author": {
    "name": "Jeff Law",
    "email": "jeffrey.law@oss.qualcomm.com",
    "time": "Mon Jun 29 14:51:24 2026 -0600"
  },
  "committer": {
    "name": "Jeff Law",
    "email": "jeffrey.law@oss.qualcomm.com",
    "time": "Mon Jun 29 14:51:24 2026 -0600"
  },
  "message": "[RISC-V] Improve logical and with some constants where high 32 bits in mask are clear\n\nI was playing around with our logical sequences on Friday spurred by a case\nthat showed up in a BZ.  In that effort I stumbled over a second class of cases\nthat\u0027s pretty easy to handle.\n\nIn general if we need to do a logical AND where the mask is just a series of on\nbits in the middle of a word, then that is at worst a 3 instruction sequence.\nLogical shift right to clear some number of low bits, logical shift left to\nclear upper bits, logical shift right to put everything into its final\nposition.  We already support this.\n\nsrliw is an interesting instruction in this space because it can clear the\nupper 32 bits and some number of low bits at the same time.  So let\u0027s take a \u0026\n0x00000000ffff0000.\n\nWe could shift \"a\" right by 16, left by 48, the right again by 16. But using\nslliw is better.  We just srliw by 16 bits to clear the upper 32 bits as well\nas the low 16 bits.  Then slli to put the bits into their final position.  This\nworks for any case where the upper 32 bits are clear and there\u0027s a run of 1s in\nthe low 32 bits ending at bit #31.\n\nWhen this applies we avoid synthesizing the constant and thus trivially reduce\nour reliance on mvconst_internal to help clean things up.  This did require\ntightening up an unnamed define_insn_and_split which tried to use zext.[hw] to\ndo bulk clearing of upper bits.  We just want it to avoid matching for cases\nwhere the upper 32 bits are clear and we have a run of 1s ending at bit 31 on\nin the mask.\n\nBootstrapped and regression tested on the c920 and K3 as well as regression\ntested on riscv64-elf and riscv32-elf.  It\u0027s worth noting this sequence doesn\u0027t\nrequire any special extension support, so it has the potential to trigger on\nthe c920.\n\nWaiting on pre-commit before moving forward.\n\ngcc/\n\t* config/riscv/riscv.cc (synthesize_and): Use srliw to handle\n\tclearing both upper and lower bits in some cases.\n\t* config/riscv/bitmanip.md (ZBA splitter using sext.w): Do not\n\tuse in cases where we can use srliw to clear those upper bits.\n\ngcc/testsuite\n\t* gcc.target/riscv/and-synthesis-1.c: New test.\n",
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