| /* Subroutines for the C front end on the PowerPC architecture. |
| Copyright (C) 2002-2018 Free Software Foundation, Inc. |
| |
| Contributed by Zack Weinberg <zack@codesourcery.com> |
| and Paolo Bonzini <bonzini@gnu.org> |
| |
| This file is part of GCC. |
| |
| GCC is free software; you can redistribute it and/or modify it |
| under the terms of the GNU General Public License as published |
| by the Free Software Foundation; either version 3, or (at your |
| option) any later version. |
| |
| GCC is distributed in the hope that it will be useful, but WITHOUT |
| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| License for more details. |
| |
| You should have received a copy of the GNU General Public License |
| along with GCC; see the file COPYING3. If not see |
| <http://www.gnu.org/licenses/>. */ |
| |
| #define IN_TARGET_CODE 1 |
| |
| #include "config.h" |
| #include "system.h" |
| #include "coretypes.h" |
| #include "target.h" |
| #include "c-family/c-common.h" |
| #include "memmodel.h" |
| #include "tm_p.h" |
| #include "stringpool.h" |
| #include "stor-layout.h" |
| #include "c-family/c-pragma.h" |
| #include "langhooks.h" |
| #include "c/c-tree.h" |
| |
| |
| |
| /* Handle the machine specific pragma longcall. Its syntax is |
| |
| # pragma longcall ( TOGGLE ) |
| |
| where TOGGLE is either 0 or 1. |
| |
| rs6000_default_long_calls is set to the value of TOGGLE, changing |
| whether or not new function declarations receive a longcall |
| attribute by default. */ |
| |
| #define SYNTAX_ERROR(gmsgid) do { \ |
| warning (OPT_Wpragmas, gmsgid); \ |
| warning (OPT_Wpragmas, "ignoring malformed #pragma longcall"); \ |
| return; \ |
| } while (0) |
| |
| void |
| rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED) |
| { |
| tree x, n; |
| |
| /* If we get here, generic code has already scanned the directive |
| leader and the word "longcall". */ |
| |
| if (pragma_lex (&x) != CPP_OPEN_PAREN) |
| SYNTAX_ERROR ("missing open paren"); |
| if (pragma_lex (&n) != CPP_NUMBER) |
| SYNTAX_ERROR ("missing number"); |
| if (pragma_lex (&x) != CPP_CLOSE_PAREN) |
| SYNTAX_ERROR ("missing close paren"); |
| |
| if (n != integer_zero_node && n != integer_one_node) |
| SYNTAX_ERROR ("number must be 0 or 1"); |
| |
| if (pragma_lex (&x) != CPP_EOF) |
| warning (OPT_Wpragmas, "junk at end of #pragma longcall"); |
| |
| rs6000_default_long_calls = (n == integer_one_node); |
| } |
| |
| /* Handle defining many CPP flags based on TARGET_xxx. As a general |
| policy, rather than trying to guess what flags a user might want a |
| #define for, it's better to define a flag for everything. */ |
| |
| #define builtin_define(TXT) cpp_define (pfile, TXT) |
| #define builtin_assert(TXT) cpp_assert (pfile, TXT) |
| |
| /* Keep the AltiVec keywords handy for fast comparisons. */ |
| static GTY(()) tree __vector_keyword; |
| static GTY(()) tree vector_keyword; |
| static GTY(()) tree __pixel_keyword; |
| static GTY(()) tree pixel_keyword; |
| static GTY(()) tree __bool_keyword; |
| static GTY(()) tree bool_keyword; |
| static GTY(()) tree _Bool_keyword; |
| static GTY(()) tree __int128_type; |
| static GTY(()) tree __uint128_type; |
| |
| /* Preserved across calls. */ |
| static tree expand_bool_pixel; |
| |
| static cpp_hashnode * |
| altivec_categorize_keyword (const cpp_token *tok) |
| { |
| if (tok->type == CPP_NAME) |
| { |
| cpp_hashnode *ident = tok->val.node.node; |
| |
| if (ident == C_CPP_HASHNODE (vector_keyword)) |
| return C_CPP_HASHNODE (__vector_keyword); |
| |
| if (ident == C_CPP_HASHNODE (pixel_keyword)) |
| return C_CPP_HASHNODE (__pixel_keyword); |
| |
| if (ident == C_CPP_HASHNODE (bool_keyword)) |
| return C_CPP_HASHNODE (__bool_keyword); |
| |
| if (ident == C_CPP_HASHNODE (_Bool_keyword)) |
| return C_CPP_HASHNODE (__bool_keyword); |
| |
| return ident; |
| } |
| |
| return 0; |
| } |
| |
| static void |
| init_vector_keywords (void) |
| { |
| /* Keywords without two leading underscores are context-sensitive, and hence |
| implemented as conditional macros, controlled by the |
| rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit |
| support, record the __int128_t and __uint128_t types. */ |
| |
| __vector_keyword = get_identifier ("__vector"); |
| C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL; |
| |
| __pixel_keyword = get_identifier ("__pixel"); |
| C_CPP_HASHNODE (__pixel_keyword)->flags |= NODE_CONDITIONAL; |
| |
| __bool_keyword = get_identifier ("__bool"); |
| C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL; |
| |
| vector_keyword = get_identifier ("vector"); |
| C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL; |
| |
| pixel_keyword = get_identifier ("pixel"); |
| C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL; |
| |
| bool_keyword = get_identifier ("bool"); |
| C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL; |
| |
| _Bool_keyword = get_identifier ("_Bool"); |
| C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL; |
| |
| if (TARGET_VADDUQM) |
| { |
| __int128_type = get_identifier ("__int128_t"); |
| __uint128_type = get_identifier ("__uint128_t"); |
| } |
| } |
| |
| /* Helper function to find out which RID_INT_N_* code is the one for |
| __int128, if any. Returns RID_MAX+1 if none apply, which is safe |
| (for our purposes, since we always expect to have __int128) to |
| compare against. */ |
| static int |
| rid_int128(void) |
| { |
| int i; |
| |
| for (i = 0; i < NUM_INT_N_ENTS; i ++) |
| if (int_n_enabled_p[i] |
| && int_n_data[i].bitsize == 128) |
| return RID_INT_N_0 + i; |
| |
| return RID_MAX + 1; |
| } |
| |
| /* Called to decide whether a conditional macro should be expanded. |
| Since we have exactly one such macro (i.e, 'vector'), we do not |
| need to examine the 'tok' parameter. */ |
| |
| static cpp_hashnode * |
| rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok) |
| { |
| cpp_hashnode *expand_this = tok->val.node.node; |
| cpp_hashnode *ident; |
| |
| /* If the current machine does not have altivec, don't look for the |
| keywords. */ |
| if (!TARGET_ALTIVEC) |
| return NULL; |
| |
| ident = altivec_categorize_keyword (tok); |
| |
| if (ident != expand_this) |
| expand_this = NULL; |
| |
| if (ident == C_CPP_HASHNODE (__vector_keyword)) |
| { |
| int idx = 0; |
| do |
| tok = cpp_peek_token (pfile, idx++); |
| while (tok->type == CPP_PADDING); |
| ident = altivec_categorize_keyword (tok); |
| |
| if (ident == C_CPP_HASHNODE (__pixel_keyword)) |
| { |
| expand_this = C_CPP_HASHNODE (__vector_keyword); |
| expand_bool_pixel = __pixel_keyword; |
| } |
| else if (ident == C_CPP_HASHNODE (__bool_keyword)) |
| { |
| expand_this = C_CPP_HASHNODE (__vector_keyword); |
| expand_bool_pixel = __bool_keyword; |
| } |
| /* The boost libraries have code with Iterator::vector vector in it. If |
| we allow the normal handling, this module will be called recursively, |
| and the vector will be skipped.; */ |
| else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword))) |
| { |
| enum rid rid_code = (enum rid)(ident->rid_code); |
| enum node_type itype = ident->type; |
| /* If there is a function-like macro, check if it is going to be |
| invoked with or without arguments. Without following ( treat |
| it like non-macro, otherwise the following cpp_get_token eats |
| what should be preserved. */ |
| if (itype == NT_MACRO && cpp_fun_like_macro_p (ident)) |
| { |
| int idx2 = idx; |
| do |
| tok = cpp_peek_token (pfile, idx2++); |
| while (tok->type == CPP_PADDING); |
| if (tok->type != CPP_OPEN_PAREN) |
| itype = NT_VOID; |
| } |
| if (itype == NT_MACRO) |
| { |
| do |
| (void) cpp_get_token (pfile); |
| while (--idx > 0); |
| do |
| tok = cpp_peek_token (pfile, idx++); |
| while (tok->type == CPP_PADDING); |
| ident = altivec_categorize_keyword (tok); |
| if (ident == C_CPP_HASHNODE (__pixel_keyword)) |
| { |
| expand_this = C_CPP_HASHNODE (__vector_keyword); |
| expand_bool_pixel = __pixel_keyword; |
| rid_code = RID_MAX; |
| } |
| else if (ident == C_CPP_HASHNODE (__bool_keyword)) |
| { |
| expand_this = C_CPP_HASHNODE (__vector_keyword); |
| expand_bool_pixel = __bool_keyword; |
| rid_code = RID_MAX; |
| } |
| else if (ident) |
| rid_code = (enum rid)(ident->rid_code); |
| } |
| |
| if (rid_code == RID_UNSIGNED || rid_code == RID_LONG |
| || rid_code == RID_SHORT || rid_code == RID_SIGNED |
| || rid_code == RID_INT || rid_code == RID_CHAR |
| || rid_code == RID_FLOAT |
| || (rid_code == RID_DOUBLE && TARGET_VSX) |
| || (rid_code == rid_int128 () && TARGET_VADDUQM)) |
| { |
| expand_this = C_CPP_HASHNODE (__vector_keyword); |
| /* If the next keyword is bool or pixel, it |
| will need to be expanded as well. */ |
| do |
| tok = cpp_peek_token (pfile, idx++); |
| while (tok->type == CPP_PADDING); |
| ident = altivec_categorize_keyword (tok); |
| |
| if (ident == C_CPP_HASHNODE (__pixel_keyword)) |
| expand_bool_pixel = __pixel_keyword; |
| else if (ident == C_CPP_HASHNODE (__bool_keyword)) |
| expand_bool_pixel = __bool_keyword; |
| else |
| { |
| /* Try two tokens down, too. */ |
| do |
| tok = cpp_peek_token (pfile, idx++); |
| while (tok->type == CPP_PADDING); |
| ident = altivec_categorize_keyword (tok); |
| if (ident == C_CPP_HASHNODE (__pixel_keyword)) |
| expand_bool_pixel = __pixel_keyword; |
| else if (ident == C_CPP_HASHNODE (__bool_keyword)) |
| expand_bool_pixel = __bool_keyword; |
| } |
| } |
| |
| /* Support vector __int128_t, but we don't need to worry about bool |
| or pixel on this type. */ |
| else if (TARGET_VADDUQM |
| && (ident == C_CPP_HASHNODE (__int128_type) |
| || ident == C_CPP_HASHNODE (__uint128_type))) |
| expand_this = C_CPP_HASHNODE (__vector_keyword); |
| } |
| } |
| else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword)) |
| { |
| expand_this = C_CPP_HASHNODE (__pixel_keyword); |
| expand_bool_pixel = 0; |
| } |
| else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__bool_keyword)) |
| { |
| expand_this = C_CPP_HASHNODE (__bool_keyword); |
| expand_bool_pixel = 0; |
| } |
| |
| return expand_this; |
| } |
| |
| |
| /* Define or undefine a single macro. */ |
| |
| static void |
| rs6000_define_or_undefine_macro (bool define_p, const char *name) |
| { |
| if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) |
| fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name); |
| |
| if (define_p) |
| cpp_define (parse_in, name); |
| else |
| cpp_undef (parse_in, name); |
| } |
| |
| /* Define or undefine macros based on the current target. If the user does |
| #pragma GCC target, we need to adjust the macros dynamically. Note, some of |
| the options needed for builtins have been moved to separate variables, so |
| have both the target flags and the builtin flags as arguments. */ |
| |
| void |
| rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, |
| HOST_WIDE_INT bu_mask) |
| { |
| if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) |
| fprintf (stderr, |
| "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX |
| ", " HOST_WIDE_INT_PRINT_HEX ")\n", |
| (define_p) ? "define" : "undef", |
| flags, bu_mask); |
| |
| /* Each of the flags mentioned below controls whether certain |
| preprocessor macros will be automatically defined when |
| preprocessing source files for compilation by this compiler. |
| While most of these flags can be enabled or disabled |
| explicitly by specifying certain command-line options when |
| invoking the compiler, there are also many ways in which these |
| flags are enabled or disabled implicitly, based on compiler |
| defaults, configuration choices, and on the presence of certain |
| related command-line options. Many, but not all, of these |
| implicit behaviors can be found in file "rs6000.c", the |
| rs6000_option_override_internal() function. |
| |
| In general, each of the flags may be automatically enabled in |
| any of the following conditions: |
| |
| 1. If no -mcpu target is specified on the command line and no |
| --with-cpu target is specified to the configure command line |
| and the TARGET_DEFAULT macro for this default cpu host |
| includes the flag, and the flag has not been explicitly disabled |
| by command-line options. |
| |
| 2. If the target specified with -mcpu=target on the command line, or |
| in the absence of a -mcpu=target command-line option, if the |
| target specified using --with-cpu=target on the configure |
| command line, is disqualified because the associated binary |
| tools (e.g. the assembler) lack support for the requested cpu, |
| and the TARGET_DEFAULT macro for this default cpu host |
| includes the flag, and the flag has not been explicitly disabled |
| by command-line options. |
| |
| 3. If either of the above two conditions apply except that the |
| TARGET_DEFAULT macro is defined to equal zero, and |
| TARGET_POWERPC64 and |
| a) BYTES_BIG_ENDIAN and the flag to be enabled is either |
| MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64" |
| target), or |
| b) !BYTES_BIG_ENDIAN and the flag to be enabled is either |
| MASK_POWERPC64 or it is one of the flags included in |
| ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target). |
| |
| 4. If a cpu has been requested with a -mcpu=target command-line option |
| and this cpu has not been disqualified due to shortcomings of the |
| binary tools, and the set of flags associated with the requested cpu |
| include the flag to be enabled. See rs6000-cpus.def for macro |
| definitions that represent various ABI standards |
| (e.g. ISA_2_1_MASKS, ISA_3_0_MASKS_SERVER) and for a list of |
| the specific flags that are associated with each of the cpu |
| choices that can be specified as the target of a -mcpu=target |
| compile option, or as the the target of a --with-cpu=target |
| configure option. Target flags that are specified in either |
| of these two ways are considered "implicit" since the flags |
| are not mentioned specifically by name. |
| |
| Additional documentation describing behavior specific to |
| particular flags is provided below, immediately preceding the |
| use of each relevant flag. |
| |
| 5. If there is no -mcpu=target command-line option, and the cpu |
| requested by a --with-cpu=target command-line option has not |
| been disqualified due to shortcomings of the binary tools, and |
| the set of flags associated with the specified target include |
| the flag to be enabled. See the notes immediately above for a |
| summary of the flags associated with particular cpu |
| definitions. */ |
| |
| /* rs6000_isa_flags based options. */ |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); |
| if ((flags & OPTION_MASK_PPC_GPOPT) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); |
| if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); |
| if ((flags & OPTION_MASK_POWERPC64) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); |
| if ((flags & OPTION_MASK_MFCRF) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); |
| if ((flags & OPTION_MASK_POPCNTB) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); |
| if ((flags & OPTION_MASK_FPRND) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); |
| if ((flags & OPTION_MASK_CMPB) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); |
| if ((flags & OPTION_MASK_MFPGPR) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); |
| if ((flags & OPTION_MASK_POPCNTD) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); |
| /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically |
| turned on in the following condition: |
| 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not |
| explicitly disabled. |
| Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to |
| have been turned on explicitly. |
| Note that the OPTION_MASK_DIRECT_MOVE flag is automatically |
| turned off in any of the following conditions: |
| 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly |
| disabled and OPTION_MASK_DIRECT_MOVE was not explicitly |
| enabled. |
| 2. TARGET_VSX is off. */ |
| if ((flags & OPTION_MASK_DIRECT_MOVE) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8"); |
| if ((flags & OPTION_MASK_MODULO) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); |
| if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) |
| rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); |
| if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) |
| rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); |
| /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on |
| in any of the following conditions: |
| 1. The command line specifies either -maltivec=le or -maltivec=be. |
| 2. The operating system is Darwin and it is configured for 64 |
| bit. (See darwin_rs6000_override_options.) |
| 3. The operating system is Darwin and the operating system |
| version is 10.5 or higher and the user has not explicitly |
| disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and |
| the compiler is not producing code for integration within the |
| kernel. (See darwin_rs6000_override_options.) |
| Note that the OPTION_MASK_ALTIVEC flag is automatically turned |
| off in any of the following conditions: |
| 1. The operating system does not support saving of AltiVec |
| registers (OS_MISSING_ALTIVEC). |
| 2. If an inner context (as introduced by |
| __attribute__((__target__())) or #pragma GCC target() |
| requests a target that normally enables the |
| OPTION_MASK_ALTIVEC flag but the outer-most "main target" |
| does not support the rs6000_altivec_abi, this flag is |
| turned off for the inner context unless OPTION_MASK_ALTIVEC |
| was explicitly enabled for the inner context. */ |
| if ((flags & OPTION_MASK_ALTIVEC) != 0) |
| { |
| const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; |
| rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); |
| rs6000_define_or_undefine_macro (define_p, vec_str); |
| |
| /* Define this when supporting context-sensitive keywords. */ |
| if (!flag_iso) |
| rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); |
| } |
| /* Note that the OPTION_MASK_VSX flag is automatically turned on in |
| the following conditions: |
| 1. TARGET_P8_VECTOR is explicitly turned on and the OPTION_MASK_VSX |
| was not explicitly turned off. Hereafter, the OPTION_MASK_VSX |
| flag is considered to have been explicitly turned on. |
| Note that the OPTION_MASK_VSX flag is automatically turned off in |
| the following conditions: |
| 1. The operating system does not support saving of AltiVec |
| registers (OS_MISSING_ALTIVEC). |
| 2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT, |
| or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the |
| OPTION_MASK_VSX flag is considered to have been turned off |
| explicitly. |
| 3. If TARGET_PAIRED_FLOAT was enabled. Hereafter, the |
| OPTION_MASK_VSX flag is considered to have been turned off |
| explicitly. |
| 4. If TARGET_AVOID_XFORM is turned on explicitly at the outermost |
| compilation context, or if it is turned on by any means in an |
| inner compilation context. Hereafter, the OPTION_MASK_VSX |
| flag is considered to have been turned off explicitly. |
| 5. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the |
| OPTION_MASK_VSX flag is considered to have been turned off |
| explicitly. |
| 6. If an inner context (as introduced by |
| __attribute__((__target__())) or #pragma GCC target() |
| requests a target that normally enables the |
| OPTION_MASK_VSX flag but the outer-most "main target" |
| does not support the rs6000_altivec_abi, this flag is |
| turned off for the inner context unless OPTION_MASK_VSX |
| was explicitly enabled for the inner context. */ |
| if ((flags & OPTION_MASK_VSX) != 0) |
| rs6000_define_or_undefine_macro (define_p, "__VSX__"); |
| if ((flags & OPTION_MASK_HTM) != 0) |
| { |
| rs6000_define_or_undefine_macro (define_p, "__HTM__"); |
| /* Tell the user that our HTM insn patterns act as memory barriers. */ |
| rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__"); |
| } |
| /* Note that the OPTION_MASK_P8_VECTOR flag is automatically turned |
| on in the following conditions: |
| 1. TARGET_P9_VECTOR is explicitly turned on and |
| OPTION_MASK_P8_VECTOR is not explicitly turned off. |
| Hereafter, the OPTION_MASK_P8_VECTOR flag is considered to |
| have been turned off explicitly. |
| Note that the OPTION_MASK_P8_VECTOR flag is automatically turned |
| off in the following conditions: |
| 1. If any of TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX |
| were turned off explicitly and OPTION_MASK_P8_VECTOR flag was |
| not turned on explicitly. |
| 2. If TARGET_ALTIVEC is turned off. Hereafter, the |
| OPTION_MASK_P8_VECTOR flag is considered to have been turned off |
| explicitly. |
| 3. If TARGET_VSX is turned off and OPTION_MASK_P8_VECTOR was not |
| explicitly enabled. If TARGET_VSX is explicitly enabled, the |
| OPTION_MASK_P8_VECTOR flag is hereafter also considered to |
| have been turned off explicitly. */ |
| if ((flags & OPTION_MASK_P8_VECTOR) != 0) |
| rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__"); |
| /* Note that the OPTION_MASK_P9_VECTOR flag is automatically turned |
| off in the following conditions: |
| 1. If TARGET_P8_VECTOR is turned off and OPTION_MASK_P9_VECTOR is |
| not turned on explicitly. Hereafter, if OPTION_MASK_P8_VECTOR |
| was turned on explicitly, the OPTION_MASK_P9_VECTOR flag is |
| also considered to have been turned off explicitly. |
| Note that the OPTION_MASK_P9_VECTOR is automatically turned on |
| in the following conditions: |
| 1. If TARGET_P9_MINMAX was turned on explicitly. |
| Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to |
| have been turned on explicitly. */ |
| if ((flags & OPTION_MASK_P9_VECTOR) != 0) |
| rs6000_define_or_undefine_macro (define_p, "__POWER9_VECTOR__"); |
| /* Note that the OPTION_MASK_QUAD_MEMORY flag is automatically |
| turned off in the following conditions: |
| 1. If TARGET_POWERPC64 is turned off. |
| 2. If WORDS_BIG_ENDIAN is false (non-atomic quad memory |
| load/store are disabled on little endian). */ |
| if ((flags & OPTION_MASK_QUAD_MEMORY) != 0) |
| rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__"); |
| /* Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is automatically |
| turned off in the following conditions: |
| 1. If TARGET_POWERPC64 is turned off. |
| Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is |
| automatically turned on in the following conditions: |
| 1. If TARGET_QUAD_MEMORY and this flag was not explicitly |
| disabled. */ |
| if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0) |
| rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__"); |
| /* Note that the OPTION_MASK_CRYPTO flag is automatically turned off |
| in the following conditions: |
| 1. If any of TARGET_HARD_FLOAT or TARGET_ALTIVEC or TARGET_VSX |
| are turned off explicitly and OPTION_MASK_CRYPTO is not turned |
| on explicitly. |
| 2. If TARGET_ALTIVEC is turned off. */ |
| if ((flags & OPTION_MASK_CRYPTO) != 0) |
| rs6000_define_or_undefine_macro (define_p, "__CRYPTO__"); |
| if ((flags & OPTION_MASK_FLOAT128_KEYWORD) != 0) |
| { |
| rs6000_define_or_undefine_macro (define_p, "__FLOAT128__"); |
| if (define_p) |
| rs6000_define_or_undefine_macro (true, "__float128=__ieee128"); |
| else |
| rs6000_define_or_undefine_macro (false, "__float128"); |
| } |
| /* OPTION_MASK_FLOAT128_HARDWARE can be turned on if -mcpu=power9 is used or |
| via the target attribute/pragma. */ |
| if ((flags & OPTION_MASK_FLOAT128_HW) != 0) |
| rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__"); |
| |
| /* options from the builtin masks. */ |
| /* Note that RS6000_BTM_PAIRED is enabled only if |
| TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired). */ |
| if ((bu_mask & RS6000_BTM_PAIRED) != 0) |
| rs6000_define_or_undefine_macro (define_p, "__PAIRED__"); |
| /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu == |
| PROCESSOR_CELL) (e.g. -mcpu=cell). */ |
| if ((bu_mask & RS6000_BTM_CELL) != 0) |
| rs6000_define_or_undefine_macro (define_p, "__PPU__"); |
| } |
| |
| void |
| rs6000_cpu_cpp_builtins (cpp_reader *pfile) |
| { |
| /* Define all of the common macros. */ |
| rs6000_target_modify_macros (true, rs6000_isa_flags, |
| rs6000_builtin_mask_calculate ()); |
| |
| if (TARGET_FRE) |
| builtin_define ("__RECIP__"); |
| if (TARGET_FRES) |
| builtin_define ("__RECIPF__"); |
| if (TARGET_FRSQRTE) |
| builtin_define ("__RSQRTE__"); |
| if (TARGET_FRSQRTES) |
| builtin_define ("__RSQRTEF__"); |
| if (TARGET_FLOAT128_TYPE) |
| builtin_define ("__FLOAT128_TYPE__"); |
| #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB |
| builtin_define ("__BUILTIN_CPU_SUPPORTS__"); |
| #endif |
| |
| if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM) |
| { |
| /* Define the AltiVec syntactic elements. */ |
| builtin_define ("__vector=__attribute__((altivec(vector__)))"); |
| builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short"); |
| builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned"); |
| |
| if (!flag_iso) |
| { |
| builtin_define ("vector=vector"); |
| builtin_define ("pixel=pixel"); |
| builtin_define ("bool=bool"); |
| builtin_define ("_Bool=_Bool"); |
| init_vector_keywords (); |
| |
| /* Enable context-sensitive macros. */ |
| cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand; |
| } |
| } |
| if (!TARGET_HARD_FLOAT || !TARGET_DOUBLE_FLOAT) |
| builtin_define ("_SOFT_DOUBLE"); |
| /* Used by lwarx/stwcx. errata work-around. */ |
| if (rs6000_cpu == PROCESSOR_PPC405) |
| builtin_define ("__PPC405__"); |
| /* Used by libstdc++. */ |
| if (TARGET_NO_LWSYNC) |
| builtin_define ("__NO_LWSYNC__"); |
| |
| if (TARGET_EXTRA_BUILTINS) |
| { |
| /* For the VSX builtin functions identical to Altivec functions, just map |
| the altivec builtin into the vsx version (the altivec functions |
| generate VSX code if -mvsx). */ |
| builtin_define ("__builtin_vsx_xxland=__builtin_vec_and"); |
| builtin_define ("__builtin_vsx_xxlandc=__builtin_vec_andc"); |
| builtin_define ("__builtin_vsx_xxlnor=__builtin_vec_nor"); |
| builtin_define ("__builtin_vsx_xxlor=__builtin_vec_or"); |
| builtin_define ("__builtin_vsx_xxlxor=__builtin_vec_xor"); |
| builtin_define ("__builtin_vsx_xxsel=__builtin_vec_sel"); |
| builtin_define ("__builtin_vsx_vperm=__builtin_vec_perm"); |
| |
| /* Also map the a and m versions of the multiply/add instructions to the |
| builtin for people blindly going off the instruction manual. */ |
| builtin_define ("__builtin_vsx_xvmaddadp=__builtin_vsx_xvmadddp"); |
| builtin_define ("__builtin_vsx_xvmaddmdp=__builtin_vsx_xvmadddp"); |
| builtin_define ("__builtin_vsx_xvmaddasp=__builtin_vsx_xvmaddsp"); |
| builtin_define ("__builtin_vsx_xvmaddmsp=__builtin_vsx_xvmaddsp"); |
| builtin_define ("__builtin_vsx_xvmsubadp=__builtin_vsx_xvmsubdp"); |
| builtin_define ("__builtin_vsx_xvmsubmdp=__builtin_vsx_xvmsubdp"); |
| builtin_define ("__builtin_vsx_xvmsubasp=__builtin_vsx_xvmsubsp"); |
| builtin_define ("__builtin_vsx_xvmsubmsp=__builtin_vsx_xvmsubsp"); |
| builtin_define ("__builtin_vsx_xvnmaddadp=__builtin_vsx_xvnmadddp"); |
| builtin_define ("__builtin_vsx_xvnmaddmdp=__builtin_vsx_xvnmadddp"); |
| builtin_define ("__builtin_vsx_xvnmaddasp=__builtin_vsx_xvnmaddsp"); |
| builtin_define ("__builtin_vsx_xvnmaddmsp=__builtin_vsx_xvnmaddsp"); |
| builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp"); |
| builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp"); |
| builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp"); |
| builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp"); |
| } |
| |
| /* Map the old _Float128 'q' builtins into the new 'f128' builtins. */ |
| if (TARGET_FLOAT128_TYPE) |
| { |
| builtin_define ("__builtin_fabsq=__builtin_fabsf128"); |
| builtin_define ("__builtin_copysignq=__builtin_copysignf128"); |
| builtin_define ("__builtin_nanq=__builtin_nanf128"); |
| builtin_define ("__builtin_nansq=__builtin_nansf128"); |
| builtin_define ("__builtin_infq=__builtin_inff128"); |
| builtin_define ("__builtin_huge_valq=__builtin_huge_valf128"); |
| } |
| |
| /* Tell users they can use __builtin_bswap{16,64}. */ |
| builtin_define ("__HAVE_BSWAP__"); |
| |
| /* May be overridden by target configuration. */ |
| RS6000_CPU_CPP_ENDIAN_BUILTINS(); |
| |
| if (TARGET_LONG_DOUBLE_128) |
| { |
| builtin_define ("__LONG_DOUBLE_128__"); |
| builtin_define ("__LONGDOUBLE128"); |
| |
| if (TARGET_IEEEQUAD) |
| { |
| /* Older versions of GLIBC used __attribute__((__KC__)) to create the |
| IEEE 128-bit floating point complex type for C++ (which does not |
| support _Float128 _Complex). If the default for long double is |
| IEEE 128-bit mode, the library would need to use |
| __attribute__((__TC__)) instead. Defining __KF__ and __KC__ |
| is a stop-gap to build with the older libraries, until we |
| get an updated library. */ |
| builtin_define ("__LONG_DOUBLE_IEEE128__"); |
| builtin_define ("__KF__=__TF__"); |
| builtin_define ("__KC__=__TC__"); |
| } |
| else |
| builtin_define ("__LONG_DOUBLE_IBM128__"); |
| } |
| |
| switch (TARGET_CMODEL) |
| { |
| /* Deliberately omit __CMODEL_SMALL__ since that was the default |
| before --mcmodel support was added. */ |
| case CMODEL_MEDIUM: |
| builtin_define ("__CMODEL_MEDIUM__"); |
| break; |
| case CMODEL_LARGE: |
| builtin_define ("__CMODEL_LARGE__"); |
| break; |
| default: |
| break; |
| } |
| |
| switch (rs6000_current_abi) |
| { |
| case ABI_V4: |
| builtin_define ("_CALL_SYSV"); |
| break; |
| case ABI_AIX: |
| builtin_define ("_CALL_AIXDESC"); |
| builtin_define ("_CALL_AIX"); |
| builtin_define ("_CALL_ELF=1"); |
| break; |
| case ABI_ELFv2: |
| builtin_define ("_CALL_ELF=2"); |
| break; |
| case ABI_DARWIN: |
| builtin_define ("_CALL_DARWIN"); |
| break; |
| default: |
| break; |
| } |
| |
| /* Vector element order. */ |
| if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) |
| builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__"); |
| else |
| builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__"); |
| |
| /* Let the compiled code know if 'f' class registers will not be available. */ |
| if (TARGET_SOFT_FLOAT) |
| builtin_define ("__NO_FPRS__"); |
| |
| /* Whether aggregates passed by value are aligned to a 16 byte boundary |
| if their alignment is 16 bytes or larger. */ |
| if ((TARGET_MACHO && rs6000_darwin64_abi) |
| || DEFAULT_ABI == ABI_ELFv2 |
| || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) |
| builtin_define ("__STRUCT_PARM_ALIGN__=16"); |
| |
| /* Generate defines for Xilinx FPU. */ |
| if (rs6000_xilinx_fpu) |
| { |
| builtin_define ("_XFPU"); |
| if (rs6000_single_float && ! rs6000_double_float) |
| { |
| if (rs6000_simple_fpu) |
| builtin_define ("_XFPU_SP_LITE"); |
| else |
| builtin_define ("_XFPU_SP_FULL"); |
| } |
| if (rs6000_double_float) |
| { |
| if (rs6000_simple_fpu) |
| builtin_define ("_XFPU_DP_LITE"); |
| else |
| builtin_define ("_XFPU_DP_FULL"); |
| } |
| } |
| } |
| |
| |
| struct altivec_builtin_types |
| { |
| enum rs6000_builtins code; |
| enum rs6000_builtins overloaded_code; |
| signed char ret_type; |
| signed char op1; |
| signed char op2; |
| signed char op3; |
| }; |
| |
| const struct altivec_builtin_types altivec_overloaded_builtins[] = { |
| /* Unary AltiVec/VSX builtins. */ |
| { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, |
| RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, |
| RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, |
| RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, |
| RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, |
| RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, |
| RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, |
| RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, |
| RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, |
| RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, |
| RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, |
| RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, |
| RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, |
| RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF, |
| RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, |
| RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, |
| RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB, |
| RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB, |
| RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, |
| RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, |
| RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF, |
| RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, |
| RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB, |
| RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, |
| |
| /* Binary AltiVec/VSX builtins. */ |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, |
| RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, |
| RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, |
| RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, |
| RS6000_BTI_unsigned_V1TI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, |
| RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ, |
| RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, |
| RS6000_BTI_unsigned_V1TI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ, |
| RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, |
| RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, |
| RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, |
| { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, |
| RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| |
| { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| |
| { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| |
| { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| |
| { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, |
| RS6000_BTI_unsigned_V16QI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, |
| RS6000_BTI_unsigned_V8HI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, |
| RS6000_BTI_unsigned_V4SI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, |
| RS6000_BTI_unsigned_V2DI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, |
| RS6000_BTI_unsigned_V16QI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, |
| RS6000_BTI_unsigned_V8HI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, |
| RS6000_BTI_unsigned_V4SI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, |
| RS6000_BTI_unsigned_V2DI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX, |
| RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0}, |
| { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE, |
| RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0}, |
| { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX, |
| RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, |
| { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 }, |
| { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP, |
| RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 }, |
| |
| { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI, |
| RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, |
| { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI, |
| RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, |
| { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF, |
| RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, |
| |
| { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI, |
| RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, |
| { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI, |
| RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, |
| { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF, |
| RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, |
| |
| { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI, |
| RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, |
| { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI, |
| RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, |
| { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF, |
| RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, |
| |
| { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI, |
| RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, |
| { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI, |
| RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, |
| { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF, |
| RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, |
| |
| { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 }, |
| { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF, |
| RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 }, |
| { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF, |
| RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI, |
| RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI, |
| RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, |
| RS6000_BTI_unsigned_V2DI, 0 }, |
| { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF, |
| RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, |
| { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI, |
| RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, |
| { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI, |
| RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, |
| { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF, |
| RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, |
| { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI, |
| RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, |
| { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI, |
| RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, |
| |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, |
| RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, |
| RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, |
| RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, |
| RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, |
| |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, |
| RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, |
| ~RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, |
| |
| /* vector float vec_ldl (int, vector float *); |
| vector float vec_ldl (int, float *); */ |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, |
| |
| /* vector bool int vec_ldl (int, vector bool int *); |
| vector bool int vec_ldl (int, bool int *); |
| vector int vec_ldl (int, vector int *); |
| vector int vec_ldl (int, int *); |
| vector unsigned int vec_ldl (int, vector unsigned int *); |
| vector unsigned int vec_ldl (int, unsigned int *); */ |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, |
| |
| /* vector bool short vec_ldl (int, vector bool short *); |
| vector bool short vec_ldl (int, bool short *); |
| vector pixel vec_ldl (int, vector pixel *); |
| vector short vec_ldl (int, vector short *); |
| vector short vec_ldl (int, short *); |
| vector unsigned short vec_ldl (int, vector unsigned short *); |
| vector unsigned short vec_ldl (int, unsigned short *); */ |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, |
| |
| /* vector bool char vec_ldl (int, vector bool char *); |
| vector bool char vec_ldl (int, bool char *); |
| vector char vec_ldl (int, vector char *); |
| vector char vec_ldl (int, char *); |
| vector unsigned char vec_ldl (int, vector unsigned char *); |
| vector unsigned char vec_ldl (int, unsigned char *); */ |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, |
| ~RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, |
| |
| /* vector double vec_ldl (int, vector double *); |
| vector double vec_ldl (int, double *); */ |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, |
| RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, |
| RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, |
| |
| /* vector long long vec_ldl (int, vector long long *); |
| vector long long vec_ldl (int, long long *); |
| vector unsigned long long vec_ldl (int, vector unsigned long long *); |
| vector unsigned long long vec_ldl (int, unsigned long long *); |
| vector bool long long vec_ldl (int, vector bool long long *); |
| vector bool long long vec_ldl (int, bool long long *); */ |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, |
| ~RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, |
| ~RS6000_BTI_unsigned_long_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 }, |
| |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, |
| ~RS6000_BTI_unsigned_long_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, |
| ~RS6000_BTI_unsigned_long_long, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, |
| RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, |
| RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB, |
| RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH, |
| RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW, |
| RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, |
| RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB, |
| RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH, |
| RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW, |
| RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW, |
| RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB, |
| RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW, |
| RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, |
| RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH, |
| RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH, |
| RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB, |
| RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW, |
| RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW, |
| RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| |
| { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, |
| RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, |
| RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, |
| RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, |
| RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF, |
| RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, |
| |
| { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI, |
| RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, |
| { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI, |
| RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, |
| { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI, |
| RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, |
| { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI, |
| RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, |
| { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF, |
| RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, |
| { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF, |
| RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, |
| |
| { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, |
| |
| { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, |
| P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, |
| P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, |
| P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, |
| P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, |
| P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI, |
| RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, |
| P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI, |
| RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| |
| { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, |
| RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, |
| RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, |
| RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, |
| RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX, |
| RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS, |
| RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS, |
| RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS, |
| RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS, |
| RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS, |
| RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS, |
| RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS, |
| RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS, |
| RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, |
| { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS, |
| RS6000_BTI_unsigned_V8HI, |
