tree f74d978318904fcbd108444f9fd12a912530e1de
parent dda0023713e7bd8944255a8a4eba8c069e9a29fa
author Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> 1771968497 +0900
committer Max Filippov <jcmvbkbc@gmail.com> 1772031250 -0800

xtensa: Add 'spaceshipsi4' insn pattern

When TARGET_SALT is configured in the Xtensa ISA, a Boolean evaluation of
LT/GT[U] between address (GP) registers can be done in a single machine
instruction, making it easy to implement the spaceship operator by sub-
tracting one from the other result.

     /* examples */
     int test0(int a, int b) {
       return a == b ? 0 : (a > b ? 1 : -1);
     }
     int test1(unsigned int a, unsigned int b) {
       return a == b ? 0 : (a > b ? 1 : -1);
     }

     ;; before (-msalt)
     test0:
     	entry	sp, 32
     	mov.n	a8, a2
     	movi.n	a2, 0
     	beq	a8, a3, .L1
     	movi.n	a2, -1
     	bge	a3, a8, .L1
     	movi.n	a2, 1
     .L1:
     	retw.n
     test1:
     	entry	sp, 32
     	mov.n	a8, a2
     	movi.n	a2, 0
     	beq	a8, a3, .L6
     	movi.n	a2, -1
     	bgeu	a3, a8, .L6
     	movi.n	a2, 1
     .L6:
     	retw.n

     ;; after (-msalt)
     test0:
     	entry	sp, 32
     	salt	a8, a2, a3
     	salt	a2, a3, a2
     	sub	a2, a2, a8
     	retw.n
     test1:
     	entry	sp, 32
     	saltu	a8, a2, a3
     	saltu	a2, a3, a2
     	sub	a2, a2, a8
     	retw.n

gcc/ChangeLog:

	* config/xtensa/xtensa.md (spaceshipsi4):
	New RTL generation pattern.