)]}' { "log": [ { "commit": "968c8e7dd702cf0c4d1932393c79d58ea4b84492", "tree": "e3d42947abe844c29777aae5a62d42d61c921c82", "parents": [ "8bfe9136680918608fe0c4af0fdf6f5fd759d0e5" ], "author": { "name": "Mikael Morin", "email": "mikael@gcc.gnu.org", "time": "Sat Aug 15 18:48:01 2026 +0200" }, "committer": { "name": "Mikael Morin", "email": "mikael@gcc.gnu.org", "time": "Sat Aug 15 18:48:01 2026 +0200" }, "message": "fortran: Dereference descriptor pointer in IS_CONTIGUOUS code [PR126892]\n\nIn the IS_CONTIGUOUS implementation, add the missing dereference to really\nhave a descriptor-typed expression, usable with the descriptor accessors.\n\nWithout this change, the pointer resulting from the evaluation of the\nIS_CONTIGUOUS argument was stabilized to a variable and then directly used\nto access the descriptor fields. This was causing an internal compiler\nerror because the descriptor accessors aren\u0027t prepared to receive a pointer.\n\n\tPR fortran/126892\n\ngcc/fortran/ChangeLog:\n\n\t* trans-intrinsic.cc (gfc_conv_is_contiguous_expr): Dereference the\n\tpointer variable before using it as descriptor.\n\ngcc/testsuite/ChangeLog:\n\n\t* gfortran.dg/is_contiguous_6.f90: New test.\n" }, { "commit": "8bfe9136680918608fe0c4af0fdf6f5fd759d0e5", "tree": "c2ba572307bbe671127c8152aaac973d8c5d5a90", "parents": [ "df494ca28d75f80b4d0b4e0b93b5d23d2092131a" ], "author": { "name": "Georg-Johann Lay", "email": "avr@gjlay.de", "time": "Sat Aug 15 18:12:34 2026 +0200" }, "committer": { "name": "Georg-Johann Lay", "email": "avr@gjlay.de", "time": "Sat Aug 15 18:13:58 2026 +0200" }, "message": "AVR: Avoid magic numbers in avr-fixed.md\n\ngcc/\n\t* config/avr/avr-fixed.md: Use constants like REG_24\n\tinstead of magic numbers like 24.\n" }, { "commit": "df494ca28d75f80b4d0b4e0b93b5d23d2092131a", "tree": "e30648e2293ca9cdc9ebc64ea1bd8f6a8a3d6661", "parents": [ "8206fe642d24f24ebb175175ac163cadd2fa2e72" ], "author": { "name": "GCC Administrator", "email": "gccadmin@gcc.gnu.org", "time": "Sat Aug 15 00:16:40 2026 +0000" }, "committer": { "name": "GCC Administrator", "email": "gccadmin@gcc.gnu.org", "time": "Sat Aug 15 00:16:40 2026 +0000" }, "message": "Daily bump." }, { "commit": "8206fe642d24f24ebb175175ac163cadd2fa2e72", "tree": "5e84704afd77cc09c1280a6ccc8ccc6228d9b67e", "parents": [ "a767a6a5609e0d0850291e2a035a8c71e9b14074" ], "author": { "name": "Pierre-Emmanuel Patry", "email": "pierre-emmanuel.patry@embecosm.com", "time": "Sat Aug 15 00:07:48 2026 +0200" }, "committer": { "name": "Pierre-Emmanuel Patry", "email": "pierre-emmanuel.patry@embecosm.com", "time": "Sat Aug 15 01:27:52 2026 +0200" }, "message": "MAINTAINERS: Add myself to rust maintainers\n\nChangeLog:\n\n\t* MAINTAINERS: Regenerate.\n\t* MAINTAINERS.yml: Add myself to rust and libgrust maintainers.\n\nSigned-off-by: Pierre-Emmanuel Patry \u003cpierre-emmanuel.patry@embecosm.com\u003e\n" }, { "commit": "a767a6a5609e0d0850291e2a035a8c71e9b14074", "tree": "3e43a33280e5edbdc8972d74a86b35618b88c9a1", "parents": [ "af0cf36fb47a704a02dd2ead5f8db5d140e45351" ], "author": { "name": "Odysseas Georgoudis", "email": "odygrd@hotmail.com", "time": "Wed Jul 22 21:47:56 2026 +0100" }, "committer": { "name": "H.J. Lu", "email": "hjl.tools@gmail.com", "time": "Sat Aug 15 06:18:20 2026 +0800" }, "message": "i386: Canonicalize PAVG builtins to IFN_AVG_CEIL [PR122715]\n\nPAVG builtins use signed vector types even though the instruction\ncomputes an unsigned average rounded up. View-convert the operands\nto unsigned vector types and canonicalize unmasked and all-ones\nmasked calls to IFN_AVG_CEIL. This exposes the calls to generic\nsimplifications while preserving masks with inactive lanes.\n\nFor modes without an IFN_AVG_CEIL optab, canonicalize only when\nequal operands allow the internal function to simplify immediately.\n\n\tPR middle-end/122715\n\ngcc/ChangeLog:\n\n\t* config/i386/i386.cc: Include \"internal-fn.h\".\n\t(ix86_gimple_fold_builtin): Canonicalize PAVG builtins to\n\tIFN_AVG_CEIL.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/i386/pr122715.c: New test.\n\t* gcc.target/i386/pr122715-2.c: New test.\n" }, { "commit": "af0cf36fb47a704a02dd2ead5f8db5d140e45351", "tree": "3011326dc570457eaa5db6dbd1c56ebe1a6dc768", "parents": [ "d5634bbbaaa5c0a23988703d0d62f66c6df561bd" ], "author": { "name": "Shreya Munnangi", "email": "smunnang@qti.qualcomm.com", "time": "Fri Aug 14 14:53:34 2026 -0600" }, "committer": { "name": "Jeff Law", "email": "jeffrey.law@oss.qualcomm.com", "time": "Fri Aug 14 14:53:34 2026 -0600" }, "message": "[PATCH][RISC-V][PR rtl-optimization/125731] Improving sequences for conditional xor with a constant\n\nThis is Shreya\u0027s work to address pr125731. I did some testing around this to\nverify riscv64-elf and riscv32-elf are happy. Testing on the K1/K3/c920 will\nfire up tonight, but not expecting significant issues there.\n\n--\n\nIn PR125731,\n\nWe are generating inefficient sequences for conditional xor with a\nconstant. Given this testcase,\n\nlong fun_not1 (int a, long b)\n{\n if (!(a \u0026 1))\n b ^\u003d 8;\n return b;\n}\n\nWe are generating:\n\nfun_not1:\n andi a5,a0,1\n mv a0,a1\n bne a5,zero,.L3\n xori a0,a1,8\n.L3:\n ret\n\nHowever, this can be simplified into a branchless sequence. One such sequence:\n\n andi a5,a0,1\n li a4,8\n czero.nez a5,a4,a5\n xor a0,a1,a5\n ret\n\nAnother form:\n\n andi a0,a0,1\n seqz t0,a0\n slli t1,t0,3\n xor a0,a1,t1\n ret\n-- I\u0027ve edited Shreya\u0027s explanation a bit --\n\nThe if-converter\u0027s get_base_reg currently returns NULL if presented with a\nconstant and that inhibits if conversion through the noce_try_cond_arith which\ncan generate more efficient sequences than generalized conditional moves. So\nthe first thing we need to do is support constants in get_base_reg.\n\nThe return value from get_base_reg is used to generate a new pseudo register,\nso if get_base_reg starts returning constants, then we\u0027re going to run into\nproblems generating the new pseudo because constants are VOIDmode.\n\nI changed the name to get_base_reg_or_constant to reflect that we are also\nhandling constants, not just returning the base registers of a reg or subreg.\nThe point where the caller uses the return value to get a mode for the new\npseudo has been changed to get the mode from the other operand of the binary\noperation.\n\nThose changes are sufficient to if-convert this example as well as enabling\nmore efficient code generation for other cases where we have a conditional\noperation where one operand is a constant.\n\nAlthough the newly generated sequence is the same number of insns, it will be\nmuch faster if the conditional branch is not easily predictable.\n\n\tPR rtl-optimization/125731\ngcc/\n\t* ifcvt.cc (get_base_reg_or_const): Renamed from get_base_reg.\n\tHandle CONST_INTs too.\n\t(noce_try_cond_arith): Use get_base_reg_or_const. Handle case where\n\tget_base_reg_or_const returns a CONST_INT.\n\ngcc/testsuite\n\t* gcc.target/riscv/pr125731.c: New test.\n" }, { "commit": "d5634bbbaaa5c0a23988703d0d62f66c6df561bd", "tree": "bebfdf7f3a9441175c748216df82a6793bcabc4d", "parents": [ "b3bca9f73eb6b29bddf5fec92e929f32675b8d20" ], "author": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Fri Aug 14 15:53:23 2026 -0400" }, "committer": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Fri Aug 14 15:53:23 2026 -0400" }, "message": "c++: INIT_EXPR trial constexpr folding\n\nThis patch adds trial constexpr folding of INIT_EXPR that mirrors the\nexisting TARGET_EXPR folding added by r15-6052. Since local copy-init\nis represented as INIT_EXPR, this addresses the xfails in\nis_constant_evaluated3{a,b}.C.\n\ngcc/cp/ChangeLog:\n\n\t* cp-gimplify.cc (cp_fold_r) \u003ccase INIT_EXPR\u003e: Add trial\n\tmaybe_constant_init logic like for TARGET_EXPR.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/opt/is_constant_evaluated3a.C: Remove xfail.\n\t* g++.dg/opt/is_constant_evaluated3b.C: Likewise.\n\nReviewed-by: Jason Merrill \u003cjason@redhat.com\u003e\n" }, { "commit": "b3bca9f73eb6b29bddf5fec92e929f32675b8d20", "tree": "8e45211eabc3ab2d2f2682ae5edf98cb4a6034c5", "parents": [ "9b0341a7a6a38912e667982003bcbfebdfb86335" ], "author": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Fri Aug 14 15:53:12 2026 -0400" }, "committer": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Fri Aug 14 15:53:12 2026 -0400" }, "message": "c++: is_const_eval init folding inside lambda scope [PR126483]\n\nHere when processing a\u0027s copy-initialization we overeagerly fold its\ninitializer as if the lambda scope is not constexpr, and thus assume\nis_constant_evaluated is false. Subsequent constant evaluation of the\nlambda gives the wrong answer due to this premature folding.\n\nThe culprit cp_fully_fold_init call is guarded by DECL_DECLARED_CONSTEXPR_P\nbut that can\u0027t be relied on for maybe-constexpr lambdas until the lambda is\nfully parsed and its body is checked as a whole for constexpr suitability.\nThis patch makes us check maybe_constexpr_fn instead, which considers such\nlambdas.\n\nThis however means we no longer fold a\u0027s copy-init even for the runtime\nversion of the lambda body, hence the is_constant_evaluated3b.C xfail.\nMaking maybe_constexpr_fn distinguish between fully parsed constexpr and\nnon-constexpr lambdas doesn\u0027t help because we don\u0027t hit this code path\nagain. And cp_fold_function doesn\u0027t fold the copy-init because it\u0027s\nrepresented as an INIT_EXPR of an AGGR_INIT_EXPR which it doesn\u0027t yet\nhandle. The subsequent patch will enable folding of INIT_EXPR\ninitializers to address this xfail.\n\n\tPR c++/126483\n\ngcc/cp/ChangeLog:\n\n\t* typeck2.cc (store_init_value): Check maybe_constexpr_fn\n\tinstead of DECL_DECLARED_CONSTEXPR_P of the function scope.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/opt/is_constant_evaluated3b.C: xfail a1 initializer\n\tfolding.\n\t* g++.dg/cpp2a/is-constant-evaluated16.C: New test.\n\nReviewed-by: Jason Merrill \u003cjason@redhat.com\u003e\n" }, { "commit": "9b0341a7a6a38912e667982003bcbfebdfb86335", "tree": "d88cd3cebebd1100c046627321f442fdd227e627", "parents": [ "038a334a1f5d28163393c15c842b4db729028a31" ], "author": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Fri Aug 14 15:53:10 2026 -0400" }, "committer": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Fri Aug 14 15:53:10 2026 -0400" }, "message": "c++: testsuite: Add some opt/is_constant_evaluated3.C variants\n\nr13-6422 added opt/is_constant_evaluated3.C to verify that we constant\nfold copy-init such as a1. (Later, r14-6506 enabled constant folding of\nthe a2-a5 inits.) r13-6422 turns out to trigger a latent bug and causes\nPR c++/126483, premature folding of is_constant_evaluated in copy-init\ninside a lambda scope.\n\nThis patch adds a couple extra variants of this test, one where the\ncontaining function is constexpr (3a) and one where it\u0027s a lambda (3b).\n\nThe new 3a.C demonstrates however that we still don\u0027t constant fold a1\u0027s\ncopy-init when inside a constexpr function scope. 3b.C demonstrates that\nwe do fold it when inside a (maybe-constexpr) lambda scope.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/opt/is_constant_evaluated3a.C: New test.\n\t* g++.dg/opt/is_constant_evaluated3b.C: New test.\n\nReviewed-by: Jason Merrill \u003cjason@redhat.com\u003e\n" }, { "commit": "038a334a1f5d28163393c15c842b4db729028a31", "tree": "4714e0bfed1b7baeea99fbf76c6688b7079d07bf", "parents": [ "0e74517b70d06105bd40c8caa6dc192b4af3ccff" ], "author": { "name": "Harald Anlauf", "email": "anlauf@gmx.de", "time": "Fri Aug 14 21:32:05 2026 +0200" }, "committer": { "name": "Harald Anlauf", "email": "anlauf@gmx.de", "time": "Fri Aug 14 21:32:05 2026 +0200" }, "message": "fortran: Fix minor memleak with GMP variables\n\nCommit r16-8564 introduced code that does not clear used GMP variables.\nFix this.\n\ngcc/fortran/ChangeLog:\n\n\t* frontend-passes.cc (inner_loop_may_be_skipped): Clear GMP variables.\n" }, { "commit": "0e74517b70d06105bd40c8caa6dc192b4af3ccff", "tree": "f914ff1316193eb66039c5d0a81614195386a45a", "parents": [ "736361789c1309e3aff154210c07653f06a769d9" ], "author": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Fri Aug 14 14:33:46 2026 -0400" }, "committer": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Fri Aug 14 14:33:46 2026 -0400" }, "message": "c++: ICE w/ maybe_warn_nodiscard on non-dep call [PR123495, PR126860]\n\nAnother latent issue uncovered by the NON_DEPENDENT_EXPR removal.\ncp_get_fndecl_from_callee, called from maybe_warn_nodiscard, tries to\nfold the templated callee via constant evaluation, but constant\nevaluation expects non-templated trees. So use fold_non_dependent_expr\nwhich instantiates templated trees beforehand. We could use f_n_d_init\nalso but there should be no difference for a result that doesn\u0027t end up\nas NULL_TREE.\n\n\tPR c++/123495\n\tPR c++/126860\n\ngcc/cp/ChangeLog:\n\n\t* cvt.cc (cp_get_fndecl_from_callee): Use fold_non_dependent_expr\n\tinstead of maybe_constant_init.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/template/non-dependent36.C: New test.\n\t* g++.dg/template/non-dependent37.C: New test.\n\nReviewed-by: Jason Merrill \u003cjason@redhat.com\u003e\n" }, { "commit": "736361789c1309e3aff154210c07653f06a769d9", "tree": "ba4b6de7c50ab7e04b96c573f4f50f4211527fa0", "parents": [ "62214130b61f48cf7cdb37c69bb14c22aea6c65a" ], "author": { "name": "Martin Uecker", "email": "uecker@tugraz.at", "time": "Sat Jul 18 23:07:31 2026 +0200" }, "committer": { "name": "Martin Uecker", "email": "uecker@gcc.gnu.org", "time": "Fri Aug 14 19:28:43 2026 +0200" }, "message": "c: fix checking ICE on pointer to a VLA of a tagged type [PR126284]\n\nRemove the check for complete types in top_array_vla_p because\nit is not correct and we may end up encountering an array with\nincomplete element type in c_verify_type. This can happen by\nreplacing structures or unions with their incomplete version when\nconstructing the canonical type.\n\n\tPR c/126284\n\ngcc/c/ChangeLog:\n\t* c-typeck.cc (top_array_vla_p): Remove check.\n\ngcc/testsuite/ChangeLog:\n\t* gcc.dg/pr126284.c: New test.\n" }, { "commit": "62214130b61f48cf7cdb37c69bb14c22aea6c65a", "tree": "e912c10e0c0e7ab44bcf1e85e7ce8660da818b71", "parents": [ "836cb4ed48c987a4a9027cb14e6b6e1edeebcaf3" ], "author": { "name": "Andrew MacLeod", "email": "amacleod@redhat.com", "time": "Thu Aug 13 13:44:09 2026 -0400" }, "committer": { "name": "Andrew MacLeod", "email": "amacleod@redhat.com", "time": "Fri Aug 14 12:00:00 2026 -0400" }, "message": "Add new relation before starting search\n\nCreate a new relation immediately. Then Calculate any known range and\nintersect the result.\n\n\tPR tree-optimization/126845\n\tgcc/\n\t* value-relation.cc (dom_oracle::search_and_merge_relation): Create\n\trelation immediately and update it later.\n\n\tgcc/testsuite/\n\t* gcc.dg/pr126845.c: New.\n" }, { "commit": "836cb4ed48c987a4a9027cb14e6b6e1edeebcaf3", "tree": "ceaaa347f89ac038d566f7c083c6a40e6163e644", "parents": [ "dc094853da348f705f95ed0a863feeeea3cd52c9" ], "author": { "name": "Andrew MacLeod", "email": "amacleod@redhat.com", "time": "Wed Aug 12 17:03:21 2026 -0400" }, "committer": { "name": "Andrew MacLeod", "email": "amacleod@redhat.com", "time": "Fri Aug 14 12:00:00 2026 -0400" }, "message": "fold_using_range should set the current query.\n\n\tPR tree-optimization/126814\n\tgcc/\n\t* gimple-range-fold.cc (fold_using_range::fold_stmt): Temporarily\n\treplace the current range query with the specified one.\n\n\tgcc/testsuite/\n\t* gcc.dg/pr126814.c: New.\n" }, { "commit": "dc094853da348f705f95ed0a863feeeea3cd52c9", "tree": "3c1c2da5da7dab2c5a7a2622945884afa1730b1e", "parents": [ "21c8ddd2cd2f3bf64225e4523e20e795083676fb" ], "author": { "name": "Andrew MacLeod", "email": "amacleod@redhat.com", "time": "Wed Aug 12 16:08:44 2026 -0400" }, "committer": { "name": "Andrew MacLeod", "email": "amacleod@redhat.com", "time": "Fri Aug 14 12:00:00 2026 -0400" }, "message": "Use logical_depth limit in fast vrp.\n\nFast VRP should use the logical_depth setting to limit exponential\nbehaviour.\n\n\tPR tree-optimization/126533\n\tgcc/\n\t* gimple-range-gori.cc (gori_name_helper): Add depth counter.\n\n\tgcc/testsuite/\n\t* gcc.dg/pr126533.c: New.\n" }, { "commit": "21c8ddd2cd2f3bf64225e4523e20e795083676fb", "tree": "4cfe08f6ad47e0c888935286ae381edcb6588c7a", "parents": [ "23797f88d1635d38ce68c8d180a0f90a1ea34740" ], "author": { "name": "Andrew MacLeod", "email": "amacleod@redhat.com", "time": "Wed Aug 12 14:34:00 2026 -0400" }, "committer": { "name": "Andrew MacLeod", "email": "amacleod@redhat.com", "time": "Fri Aug 14 11:59:59 2026 -0400" }, "message": "Limit the number of iterations in phi analyzer.\n\nThe phi analyzer attempts to provide initial values for cyclic PHIs by\nsimulating the modifer by the number of bits of precision. _BitInt\nobjects can be very large, and it is pointless to try to simulate them\nthat many ttimes.\n\n\tPR tree-optimization/126538\n\tgcc/\n\t* gimple-range-phi.cc (phi_group::calculate_using_modifier): Limit the\n\titeration upper bound to MAX_FIXED_MODE_SIZE.\n\n\tgcc/testsuite/\n\t* gcc.dg/pr126538.c: New.\n" }, { "commit": "23797f88d1635d38ce68c8d180a0f90a1ea34740", "tree": "bf979874fa76ed950208351330f1945b1695ad9f", "parents": [ "dcf34067a80904e66a91db127f39f27fdb1b6ee5" ], "author": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Mon Aug 10 20:41:36 2026 +0200" }, "committer": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Fri Aug 14 17:55:10 2026 +0200" }, "message": "match.pd: fold the inequality spelling of divisibility\n\nGCC folds:\n\n x / y * y \u003d\u003d x\n\nto:\n\n x % y \u003d\u003d 0\n\nApply the same simplification to inequality.\n\n int divisible_by_3 (unsigned int x)\n {\n return x / 3 * 3 !\u003d x;\n }\n\naarch64 -O2:\n\nbefore:\n\n\tdivisible_by_3:\n\t\tmov\tw1, 43691\n\t\tmovk\tw1, 0xaaaa, lsl 16\n\t\tumull\tx1, w0, w1\n\t\tlsr\tx1, x1, 33\n\t\tadd\tw1, w1, w1, lsl 1\n\t\tcmp\tw1, w0\n\t\tcset\tw0, ne\n\t\tret\n\nafter:\n\n\tdivisible_by_3:\n\t\tmov\tw1, 43691\n\t\tmovk\tw1, 0xaaaa, lsl 16\n\t\tmul\tw0, w0, w1\n\t\tmov\tw1, 1431655765\n\t\tcmp\tw0, w1\n\t\tcset\tw0, hi\n\t\tret\n\nBootstrapped and tested on aarch64-none-linux-gnu.\n\ngcc/ChangeLog:\n\n\t* match.pd (x / y * y \u003d\u003d x): Extend to inequality.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/tree-ssa/divmul-mod-1.c: New test.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n" }, { "commit": "dcf34067a80904e66a91db127f39f27fdb1b6ee5", "tree": "05e136e33c506bb7223f85395d5d8c3c6075e272", "parents": [ "3620be7514366af9ffe8af26082c3a87113fad01" ], "author": { "name": "Iain Sandoe", "email": "iain@sandoe.co.uk", "time": "Fri Aug 14 15:14:12 2026 +0100" }, "committer": { "name": "Iain Sandoe", "email": "iain@sandoe.co.uk", "time": "Fri Aug 14 15:14:12 2026 +0100" }, "message": "testsuite, X86: Fix missing U_L_P on pr126293-1b.c.\n\nThese new tests were failing on darwin because of the missing user\nlabel prefix.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/i386/pr126293-1b.c: Account for USER_LABEL_PREFIX.\n\t* gcc.target/i386/pr126293-1c.c: Likwise.\n\nSigned-off-by: Iain Sandoe \u003ciain@sandoe.co.uk\u003e\n" }, { "commit": "3620be7514366af9ffe8af26082c3a87113fad01", "tree": "f64a918f47be04d8c933ba699978a2fa5b7428d5", "parents": [ "c7282ce59753dd809ca567d045dc356d56b88fe2" ], "author": { "name": "Iain Sandoe", "email": "iain@sandoe.co.uk", "time": "Fri Aug 14 14:44:49 2026 +0100" }, "committer": { "name": "Iain Sandoe", "email": "iain@sandoe.co.uk", "time": "Fri Aug 14 14:44:49 2026 +0100" }, "message": "testsuite, Darwin: Update cfstring testa to account for fix in [PR126723]\n\nThese now need to handle linker-visible string lables.\n\n\tPR target/126723\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/torture/darwin-cfstring-3.C: Allow linker-visible\n\tstring labels.\n\t* gcc.dg/torture/darwin-cfstring-3.c: Likewise.\n\nSigned-off-by: Iain Sandoe \u003ciain@sandoe.co.uk\u003e\n" }, { "commit": "c7282ce59753dd809ca567d045dc356d56b88fe2", "tree": "c9a7dc028e039d1e8ecc8192137adfc444336788", "parents": [ "654eb1f70643a2c57b3c6a31c250c1213a23aa4f" ], "author": { "name": "LIU Hao", "email": "lh_mouse@126.com", "time": "Mon Aug 10 13:56:09 2026 +0800" }, "committer": { "name": "Jonathan Yong", "email": "10walls@gmail.com", "time": "Fri Aug 14 13:23:52 2026 +0000" }, "message": "gcc/mingw32: Do not export `HOST_EXTRA_OBJS_SYMBOL`\n\nWhen building with `--enable-plugin`, the linker is passed `--export-all-symbols`\nso it attempts to export `HOST_EXTRA_OBJS_SYMBOL` which is an artificial symbol\nand is not prefixed with an underscore. For i686, the convention is that if the\nlinker is told to export `foo`, it looks for `_foo`. Therefore in this case it\nattempts to export `_HOST_EXTRA_OBJS_SYMBOL` which isn\u0027t defined:\n\n ld.exe: cannot export HOST_EXTRA_OBJS_SYMBOL: symbol not found\n collect2.exe: error: ld returned 1 exit status\n\nSince this symbol is only used to create a reference to pull in the manifest\nresource for an image, the fix is to mark it as `visibility(\"hidden\")` so it\nwill not be exported, despite `--export-all-symbols`.\n\nIn addition, since this is a C++ file, `extern \"C\"` is added for correctness.\n\ngcc/ChangeLog:\n\n\t* config/i386/sym-mingw32.cc: Add `extern \"C\"` and `visibility(\"hidden\")`.\n\nSigned-off-by: Jonathan Yong \u003c10walls@gmail.com\u003e\n" }, { "commit": "654eb1f70643a2c57b3c6a31c250c1213a23aa4f", "tree": "846034d703231a0a4f35e6a17988def8ac310d3c", "parents": [ "34fd4c49fbe6ff643fc6f5f2cccca03c86535ee0" ], "author": { "name": "Jason Merrill", "email": "jason@redhat.com", "time": "Tue Aug 11 16:12:10 2026 -0400" }, "committer": { "name": "Jason Merrill", "email": "jason@redhat.com", "time": "Fri Aug 14 09:21:57 2026 -0400" }, "message": "c++: constexpr class access in generic lambda [PR126754]\n\nWe don\u0027t want to see TARGET_EXPR in template trees because it\u0027s an\nimplementation detail, not a representation of the source. But constant\nevaluation normally represents a constant class value with a TARGET_EXPR.\nLet\u0027s not do the latter in a template.\n\n\tPR c++/126754\n\ngcc/cp/ChangeLog:\n\n\t* constexpr.cc (cxx_eval_outermost_constant_expr): Don\u0027t\n\twrap in TARGET_EXPR when processing_template_decl.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/cpp1y/constexpr-lambda2.C: New test.\n" }, { "commit": "34fd4c49fbe6ff643fc6f5f2cccca03c86535ee0", "tree": "4880136859f08c3a088fa23fe27054112b5af1bb", "parents": [ "39d3259d193d13dc60b9ad12c492274ee220eb8b" ], "author": { "name": "Jason Merrill", "email": "jason@redhat.com", "time": "Tue Aug 04 19:45:17 2026 -0400" }, "committer": { "name": "Jason Merrill", "email": "jason@redhat.com", "time": "Fri Aug 14 09:21:36 2026 -0400" }, "message": "c++: clarify reshape_init designator handling\n\nWhile looking at r17-3010, I found the handling of designators in\nreshape_init* unclear, particularly in reshape_init_r. Jakub\u0027s patch\nrecurses directly from reshape_init_class to itself to avoid this confusion.\n\nWith this patch, if we see a designator in reshape_init_r, it designates a\nmember of TYPE, which means brace elision if !first_initializer_p. For this\nto be true I needed to adjust reshape_init_array_1 to use\nreshape_single_init from c++/103337. And then if we see a designator and\nTYPE is a class or array, we know we\u0027re initializing an element so we don\u0027t\nconsider initializing TYPE directly.\n\ngcc/cp/ChangeLog:\n\n\t* decl.cc (reshape_single_init): Declare sooner.\n\t(reshape_init_array_1): Use it.\n\t(reshape_init_class): Drop \"subclass\" case.\n\t(reshape_init_r): d-\u003ecur-\u003eindex always means initializing\n\tan element.\n" }, { "commit": "39d3259d193d13dc60b9ad12c492274ee220eb8b", "tree": "90cc7ad01211ec097d562297195cbb7d4131b803", "parents": [ "478c1857b4afb88d7f69a4c79158350908fa8eed" ], "author": { "name": "Robert Dubner", "email": "rdubner@symas.com", "time": "Fri Aug 14 08:33:50 2026 -0400" }, "committer": { "name": "Robert Dubner", "email": "rdubner@symas.com", "time": "Fri Aug 14 08:52:02 2026 -0400" }, "message": "cobol: Route MOVE \u003cintermediate_e\u003e to __gg__move().\n\nAn attempt to create GENERIC that moves intermediate_e values to various\ntargets has proved unsatisfactory. Thousands of such statements, with\ntheir many necessary conditional tests, result in poor middle-end\nbehavior for reasons that have yet to be investigated. Calling the\nlibrary routine results in much better behavior, with only hints of\nquadratic time appearing in functions with tens of thousands of\nstatements.\n\ngcc/cobol/ChangeLog:\n\n\t* move.cc (mh_binary_to_numdisp): Pass intermediates to __gg__move.\n\t(mh_binary_to_packed): Likewise.\n\t(mh_to_binary): Likewise.\n\t(copy_intermediate_into_place): Eliminate.\n" }, { "commit": "478c1857b4afb88d7f69a4c79158350908fa8eed", "tree": "6332aa500f028028c31a17c050a16395f8f436e6", "parents": [ "c8545a3143330983e51d913f0a01187258b14510" ], "author": { "name": "Hans-Peter Nilsson", "email": "hp@axis.com", "time": "Fri Aug 14 01:33:12 2026 +0000" }, "committer": { "name": "Hans-Peter Nilsson", "email": "hp@gcc.gnu.org", "time": "Fri Aug 14 14:42:07 2026 +0200" }, "message": "testsuite/gfortran.dg: Gate tests on effective_target fd_truncate\n\nI usually spot these kind of test-case warts not when tests are added,\ni.e. failing at introduction for non-fd_truncate targets such as\ncris-elf, but only when tests appear to regress, such as was recently\nthe case for namelist_101.f90. That test had a typo corrected in its\ndg-do directive, such that it actually became dg-do run instead of\njust defaulting to dg-do compile, and then failed because the\nformatting ends up calling raw_truncate, triggering the self-marking\noutput.\n\nTo wit, without this patch, the edited test-cases fail for\nnon-effective-target fd_truncate targets, i.e. targets that don\u0027t\nsupport chsize or ftruncate. See also\nlibgfortran/io/unix.c:raw_truncate. Similar changes where done in\n2008, 2019, and 2024.\n\n2026-08-14 Hans-Peter Nilsson \u003chp@axis.com\u003e\n\n\t* gfortran.dg/endfile_5.f90, gfortran.dg/namelist_101.f90,\n\tgfortran.dg/namelist_104.f90, gfortran.dg/unsigned_10.f90,\n\tgfortran.dg/unsigned_2.f90, gfortran.dg/unsigned_5.f90,\n\tgfortran.dg/utf8_3.f03: Gate test on effective_target\n\tfd_truncate.\n" }, { "commit": "c8545a3143330983e51d913f0a01187258b14510", "tree": "862f4255e547b45850b2b26fe3090ba995a1b7bd", "parents": [ "e5efa9eff99da897f0bbd69455d8f7856985b2db" ], "author": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Fri Aug 14 12:16:41 2026 +0200" }, "committer": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Fri Aug 14 13:09:32 2026 +0200" }, "message": "tree-optimization/126865 - SLP node with trapping stmt in wrong BB\n\nThe following fixes a SLP discovery issue where we fail to properly\nensure that when there\u0027s a trapping stmt all stmts of a node belong\nto the same BB.\n\n\tPR tree-optimization/126865\n\t* tree-vect-slp.cc (vect_build_slp_tree_1): Track common\n\tBB and whether there\u0027s any trapping stmt in the matching set\n\tand verify the same BB constraint after we\u0027ve seen all stmts.\n\n\t* gcc.dg/vect/bb-slp-pr126865.c: New testcase.\n\t* gcc.dg/vect/bb-slp-pr100778-1.c: Adjust.\n" }, { "commit": "e5efa9eff99da897f0bbd69455d8f7856985b2db", "tree": "00ad64ff28e8c7a696a38dfc3c9327a0ce08c5cd", "parents": [ "2026474385dc23e9896577db08d963bc3a96f256" ], "author": { "name": "Thomas Schwinge", "email": "tschwinge@baylibre.com", "time": "Tue Jul 28 20:46:16 2026 +0200" }, "committer": { "name": "Thomas Schwinge", "email": "tschwinge@baylibre.com", "time": "Fri Aug 14 12:38:51 2026 +0200" }, "message": "libgomp: Revise libgomp/Fortran support conditionals\n\nSubversion r152931 (Git commit 0046b1a727f73f0848733e28219069426b2dc218)\n\"Fix libgomp without --enable-languages\u003dfortran\", and its follow-up\nSubversion r156232 (Git commit d0709b6aeec6b00e71011502fa311751fc138147)\n\"configure.ac: Test for executability of GFORTRAN\",\nSubversion r156264 (Git commit 2122aa973ed2c829caee5b010a60ad01922a3650)\n\"configure.ac: Test for executability of _the first word_ of GFORTRAN\"\nfixed the libgomp target library build in case that\n\u0027--enable-languages\u003dfortran\u0027 was not in effect: in that case, disable\nlibgomp/Fortran support.\n\nThese changes certainly do the right thing in GCC configurations where\n\u0027$GFORTRAN\u0027 would be expected to be \"just compiled\" (built with the GCC\ntop-level build system). However, in case that it\u0027s \"pre-installed\" (provided\nexternally, as determined by the GCC top-level build system), these changes\ndidn\u0027t work, and instead kept libgomp/Fortran support disabled, instead of\nenabling it. \"Pre-installed\" \u0027GFORTRAN\u003d\"x86_64-w64-mingw32-gfortran [...]\"\u0027 is\nnot accepted by the current \u0027test -x [...]\u0027 check, for instance, as discussed\nin \"libgomp: Fix gfortran detection when program is found via PATH\",\n\u003chttps://inbox.sourceware.org/20260529021023.9764-1-peter0x44@disroot.org\u003e\n\u003chttps://forge.sourceware.org/gcc/gcc/pulls/172\u003e,\n\u003chttps://inbox.sourceware.org/bmm.hj9f44xa6a.gcc.gcc-TEST.Peter0x44.172.1.0@forge-stage.sourceware.org\u003e.\n\nThat proposed \"libgomp: Fix gfortran detection when program is found via PATH\"\npatch has the issue that it picks up the \"gfortran [...] found via PATH\" also\nin the case when GCC is configured without \u0027--enable-languages\u003dfortran\u0027 in\neffect, and it then still builds and installs the libgomp/Fortran support files\nin GCC configurations without Fortran support enabled.\n\nInstead of \"libgomp: Fix gfortran detection when program is found via PATH\" as\nproposed, we may revise libgomp/Fortran support conditionals generally, and\nhandle that in a conceptually simpler way: revert the three aforementioned\ncommits (in other words: simply again assign \u0027FC\u003d\"$GFORTRAN\"\u0027 (like\n\u0027libgfortran/configure.ac\u0027 also is doing), and conditionalize \u0027USE_FORTRAN\u0027 on\nwhether \u0027--enable-languages\u003dfortran\u0027 is in effect. In other words: in case\nthat \u0027--enable-languages\u003dfortran\u0027 is in effect, assume that the\n\u0027GFORTRAN\u003d[...]\u0027 passed to the libgomp build is functional -- no matter where\nit\u0027s coming from: \"just compiled\" or \"pre-installed\".\n\n\tPR libgomp/41418\n\tlibgomp/\n\t* configure.ac (FC): Revert ealier changes; just set to \u0027\"$GFORTRAN\"\u0027.\n\t(USE_FORTRAN): Conditionalize on \u0027--enable-languages\u003dfortran\u0027 being in\n\teffect.\n\t* configure: Regenerate.\n\nReported-by: Peter Damianov \u003cpeter0x44@disroot.org\u003e\n" }, { "commit": "2026474385dc23e9896577db08d963bc3a96f256", "tree": "0b1891de8eed44da3a42831fc3d710c51b7ceb17", "parents": [ "d42b8b15aa9f246293c976f141df1c1936d93dc6" ], "author": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Fri Aug 14 11:14:00 2026 +0200" }, "committer": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Fri Aug 14 12:29:43 2026 +0200" }, "message": "tree-optimization/126862 - fix live lane extract dominance check for PHIs\n\nWe were not correctly verifying dominance of the vector definition\nwith the scalar use in case of PHI use stmts. We have to ensure\nthe respective PHI edge source can reach the definition.\n\n\tPR tree-optimization/126862\n\t* tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): For PHI\n\tuses verify dominance to the PHI use edge source.\n\n\t* gcc.dg/vect/bb-slp-pr126862.c: New testcase.\n" }, { "commit": "d42b8b15aa9f246293c976f141df1c1936d93dc6", "tree": "787218082181649f246929d33f98b06b2779a6b3", "parents": [ "b190388bad47b1d3507abd52dc2a07f39a899984" ], "author": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Fri Aug 14 10:26:00 2026 +0200" }, "committer": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Fri Aug 14 12:20:27 2026 +0200" }, "message": "tree-optimization/126861 - ICE with SLP schedule at explicit region start\n\nWe cannot use a random stmt at region start as marker as that might\neventually be a control stmt. Instead use NULL to mark region\nstart as documented.\n\n\tPR tree-optimization/126861\n\t* tree-vect-slp.cc (vect_schedule_slp_node): Use NULL for\n\tscheduling at region start.\n\n\t* g++.dg/vect/slp-pr126861.cc: New testcase.\n" }, { "commit": "b190388bad47b1d3507abd52dc2a07f39a899984", "tree": "781b2dac17b5a098e9e358bce8ab9f13a29fbb35", "parents": [ "6a000bf53e6f42cff3774822227f47e39d2b76d5" ], "author": { "name": "Reshma Roy", "email": "Reshma.Roy@amd.com", "time": "Tue Aug 11 11:48:05 2026 +0530" }, "committer": { "name": "vekumar", "email": "Venkataramanan.Kumar@amd.com", "time": "Fri Aug 14 15:35:06 2026 +0530" }, "message": "match.pd: Fold umin(a, 1) | umin(b, 1) into umin(a | b, 1) [PR126646]\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/126646\n\t* match.pd: Fold umin(a, 1) | umin(b, 1) into umin(a | b, 1).\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/tree-ssa/pr126646-1.c: New test.\n\t* gcc.dg/tree-ssa/pr126646-2.c: New test.\n" }, { "commit": "6a000bf53e6f42cff3774822227f47e39d2b76d5", "tree": "8c58682401587ca89d8d563db9c4c04051cfa111", "parents": [ "bbf1dfa9da862caadf97ebf9a21b877b1553dbf4" ], "author": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Fri Aug 14 10:57:17 2026 +0200" }, "committer": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Fri Aug 14 11:57:48 2026 +0200" }, "message": "tree-optimization/126852 - verify SLP schedule also for PHIs\n\nWe have to verify the PHI argument nodes insertion place dominates\nthe PHI argument edge sources.\n\n\tPR tree-optimization/126852\n\t* tree-vect-slp.cc (vect_schedule_slp_node): Verify schedule\n\tfor PHIs.\n\n\t* gcc.dg/vect/bb-slp-pr126852.c: New testcase.\n" }, { "commit": "bbf1dfa9da862caadf97ebf9a21b877b1553dbf4", "tree": "cf788ad3bb47c2712bc82e0db41f3de13996efb3", "parents": [ "4f1c60804531475ad86206f3cc298da6ce001d83" ], "author": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Jul 29 21:27:05 2026 +0200" }, "committer": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Fri Aug 14 11:29:49 2026 +0200" }, "message": "match.pd: combine a pair of vector comparisons against zero\n\nA lane of A | B is zero exactly when the corresponding lanes of A and of B\nare both zero, so\n\n (A \u003d\u003d 0) \u0026 (B \u003d\u003d 0) -\u003e (A | B) \u003d\u003d 0\n\nand the De Morgan dual for inequality. The existing scalar rule already\nimplements this identity. Extend it to vector integers and use a view\nconversion when the operands differ only in element signedness. Extend the\nrelated all-ones rule in the same way.\n\n typedef int v4si __attribute__((vector_size (16)));\n v4si f (v4si a, v4si b) { return (a \u003d\u003d 0) \u0026 (b \u003d\u003d 0); }\n\naarch64 -O3 before:\n\n\tcmeq\tv0.4s, v0.4s, #0\n\tcmeq\tv1.4s, v1.4s, #0\n\tand\tv0.16b, v0.16b, v1.16b\n\nafter:\n\n\torr\tv0.16b, v0.16b, v1.16b\n\tcmeq\tv0.4s, v0.4s, #0\n\nAdd vector_nop_conversion_p for the element-wise property shared by these\nrules and the existing nop_convert matcher.\n\nBootstrapped and tested on aarch64-none-linux-gnu.\n\ngcc/ChangeLog:\n\n\t* match.pd (nop_convert): Use vector_nop_conversion_p.\n\t((A \u003d\u003d 0) \u0026 (B \u003d\u003d 0), (A !\u003d 0) | (B !\u003d 0)): Extend the\n\texisting simplifications to vector operands.\n\t((A \u003d\u003d -1) \u0026 (B \u003d\u003d -1), (A !\u003d -1) | (B !\u003d -1)): Likewise.\n\t* tree.cc (vector_nop_conversion_p): New function.\n\t* tree.h (vector_nop_conversion_p): Declare.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/tree-ssa/vec-mask-zero-1.c: New test.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n" }, { "commit": "4f1c60804531475ad86206f3cc298da6ce001d83", "tree": "587bf5ec3a8f2e859e2d274598a4b69509806019", "parents": [ "8d004ef91c4f7c315519975ffaec78d28d4a21ff" ], "author": { "name": "Paul Thomas", "email": "pault@gcc.gnu.org", "time": "Wed Aug 12 17:24:12 2026 +0100" }, "committer": { "name": "Paul Thomas", "email": "pault@gcc.gnu.org", "time": "Fri Aug 14 09:22:42 2026 +0100" }, "message": "Fortran: Fix ICE with recursively defined derived type [PR104048]\n\n2026-08-14 Paul Thomas \u003cpault@gcc.gnu.org\u003e\n\ngcc/fortran\n\tPR fortran/104048\n\t* trans-array.cc (structure_alloc_comps): Extend the wrapper\n\tmechanism for same type allocatable arrays to scalars, creating\n\tdescriptors for them and passing to the deep copy library fcn..\n\ngcc/testsuite/\n\tPR fortran/104048\n\t* gfortran.dg/recursive_alloc_comp_7.f90: New test.\n\t* gfortran.dg/recursive_alloc_comp_8.f90: New test.\n" }, { "commit": "8d004ef91c4f7c315519975ffaec78d28d4a21ff", "tree": "8a0cf9def75b9ed4be73a01a72b0c6987dab9606", "parents": [ "b6477e6c4efd6df2719190cb048cf300ff31af46" ], "author": { "name": "Andrea Pinski", "email": "andrew.pinski@oss.qualcomm.com", "time": "Mon Jul 27 23:02:07 2026 -0700" }, "committer": { "name": "Andrea Pinski", "email": "andrew.pinski@oss.qualcomm.com", "time": "Thu Aug 13 23:52:58 2026 -0700" }, "message": "match: Try to remove casts for `(int)-(unsigned)a`[PR107765]\n\nThis adds some extra checks to see if we can remove the casts\nfor signed integer overflow reasons while doing a negative.\nThis is needed more due to the recent patch which adds them\nin some cases.\n\nThis also changes TYPE_UNSIGNED to be TYPE_OVERFLOW_WRAPS to\nallow this to happen with -fwrapv too.\n\nChanges since v1:\n* Use expr_not_equal_to and simplify the if stmt.\nAlso use TYPE_OVERFLOW_WRAPS instead of TYPE_UNSIGNED.\n\nBootstrapped and tested on x86_64-linux-gnu.\n\n\tPR tree-optimization/107765\n\ngcc/ChangeLog:\n\n\t* match.pd (`(cast)-(cast)a`): Expand to\n\tuse expr_not_equal_to of INT_MIN.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/tree-ssa/neg-cast-1.c: New test.\n\t* gcc.dg/tree-ssa/neg-cast-4.c: New test.\n\nSigned-off-by: Andrea Pinski \u003candrew.pinski@oss.qualcomm.com\u003e\n" }, { "commit": "b6477e6c4efd6df2719190cb048cf300ff31af46", "tree": "94ecc1890fcf3ffe7c9679d7e839526cb9988ef8", "parents": [ "729eb68a0021bd37acff6a07a505b89687b974b9" ], "author": { "name": "Longjun Luo", "email": "luolongjuna@gmail.com", "time": "Thu Jul 23 00:01:50 2026 +0800" }, "committer": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Fri Aug 14 08:11:18 2026 +0200" }, "message": "debug/126355 - preserve debug info for IPA ICF wrappers\n\nWhen IPA ICF keeps a distinct symbol for an address-taken function by\nreplacing its body with a wrapper, cgraph_node::create_wrapper reuses the\noriginal function declaration and its early debug DIE.\n\ncreate_wrapper then calls expand_thunk with force_gimple_thunk set. Forced\nGIMPLE thunks are normally created after early debug, so expand_thunk marks\ntheir declarations ignored. For an ICF wrapper this also prevents final\ndebug emission from attaching the wrapper address to the existing DIE.\nThe wrapper consequently has code and an STT_FUNC symbol but no\naddress-bearing DW_TAG_subprogram DIE.\n\nPreserve the declaration\u0027s original DECL_IGNORED_P value across forced\nGIMPLE thunk expansion in create_wrapper. Declarations that were already\nignored remain ignored, while an original source declaration can receive\nits final address information.\n\nTested on x86_64-pc-linux-gnu with the new gcc.dg/debug/dwarf2 test. The\ntest fails before the change and passes afterwards.\n\n\tPR debug/126355\n\ngcc/ChangeLog:\n\n\t* cgraphunit.cc (cgraph_node::create_wrapper): Preserve\n\tDECL_IGNORED_P across forced GIMPLE thunk expansion.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/debug/dwarf2/pr126355.c: New test.\n\nSigned-off-by: Longjun Luo \u003cluolongjuna@gmail.com\u003e\n" }, { "commit": "729eb68a0021bd37acff6a07a505b89687b974b9", "tree": "845c0326b603173182e0e90b5b9cbd0b67836558", "parents": [ "0cfd3de946cedafc0948fe4fde5a015c63b8993c" ], "author": { "name": "Naveen", "email": "naveen.siddegowda@oss.qualcomm.com", "time": "Thu Aug 13 22:00:54 2026 -0700" }, "committer": { "name": "Naveen", "email": "naveen.siddegowda@oss.qualcomm.com", "time": "Thu Aug 13 22:00:54 2026 -0700" }, "message": "tree-optimization: Fold canonicalized vector min/max conditionals [PR98602]\n\nThe existing VEC_COND_EXPR min/max patterns require the comparison and result\nconstants to be equal so they do not recognize this canonicalized form.\nAdd patterns for the GE/LT forms produced from negative signed maximum\nexpressions and for the LE/GT forms produced from positive signed or unsigned\nminimum expressions. Handle both normal and reversed conditional arms.\nThe off-by-one check is performed elementwise so the transform is not\nrestricted to uniform vector constants.\n\nThis also handles non-uniform vector constants such as:\nX \u003e\u003d { -99, -98 } ? X : { -100, -99 }\nwhich can be folded to:\nMAX_EXPR \u003cX, { -100, -99 }\u003e\nwhen each comparison element is exactly one greater than the corresponding\nresult element. Variable-length vector constants are handled when the two\nconstants have matching VECTOR_CST encodings.\n\ngcc/ChangeLog:\n\tPR tree-optimization/98602\n\t* match.pd (vec_cond (cmp @0 VECTOR_CST@1) @0 VECTOR_CST@2):\n\tNew simplification.\n\t(vec_cond (cmp @0 VECTOR_CST@1) VECTOR_CST@2 @0): Likewise.\n\t* tree.cc (record_uniform_integer_difference): New helper.\n\t(uniform_vector_difference_p): New function.\n\t* tree.h (uniform_vector_difference_p): Declare.\n\ngcc/testsuite/ChangeLog:\n\tPR tree-optimization/98602\n\t* g++.dg/tree-ssa/pr98602.C: New test.\n\t* g++.target/aarch64/sve/max_1.C: Remove fixed XFAILs.\n\t* g++.target/aarch64/sve/min_1.C: Likewise.\n\nSigned-off-by: Naveen \u003cnaveen.siddegowda@oss.qualcomm.com\u003e\n" }, { "commit": "0cfd3de946cedafc0948fe4fde5a015c63b8993c", "tree": "78a59b33d224083ed03d87a283e0bf3c7b84f761", "parents": [ "1b9420378621b9b882243f4ccb8c2f8fdd8c979b" ], "author": { "name": "Jeff Law", "email": "jeffrey.law@oss.qualcomm.com", "time": "Thu Aug 13 21:22:57 2026 -0600" }, "committer": { "name": "Jeff Law", "email": "jeffrey.law@oss.qualcomm.com", "time": "Thu Aug 13 21:24:49 2026 -0600" }, "message": "[RISC-V][PR target/108031] Adjust cost of LO_SUM expression slightly\n\nSo this is the second part to pr108031.\n\nOriginally I thought this was going to be related to Shreya\u0027s work on fixing\nvarious cost model goofs in the RISC-V backend and that if we fixed the cost\nmodeling that the right things would just happen. Essentially what I\u0027ve had\nher focused on is cases where we have a single cycle ALU insn, but the reported\ncost is anything but 4. Lots of these issues have been clustered around\nembedded extensions, complex RTL for bitmanip instructions, symbolic addresses,\netc. I figured the costing issue with 108031 would be related.\n\nBut it\u0027d been a while since I did that very quick triage, so I went back and\ntook a closer look at the behavior inside CSE; that\u0027s when it became clear that\nthe LO_SUM expression and related value equivalent were reporting the same\ncost. In that scenario CSE (reasonably) chooses to keep things as-is to avoid\ngratuitous IL changes.\n\nSo we need the LO_SUM expression to cost higher than a simple PLUS, even though\nthey both collapse into addi/add insns. It\u0027s not as crazy at it might seem as\nanytime we can get rid of the LO_SUM form, we\u0027re likely going to get rid of the\nHIGH expression as well. Other ports cost symbolics much higher and the RISC-V\nport may want to follow suit at some point, but for now we can just add a\nsingle unit to the LO_SUM expression cost and all the right things happen --\nhopefully with no fallout.\n\nThis has been tested on riscv32-elf and riscv64-elf. Bootstraps on the K3 and\nc920 will run overnight, but I don\u0027t expect any issues. Pushing to the trunk.\n\n\tPR target/108031\ngcc/\n\t* config/riscv/riscv.cc (riscv_rtx_costs): Bump the cost of a LO_SUM\n\tby one unit to encourage use of related values instead of the symbolic\n\tform.\n\ngcc/testsuite\n\t* gcc.target/riscv/pr108031-2.c: New test.\n" }, { "commit": "1b9420378621b9b882243f4ccb8c2f8fdd8c979b", "tree": "21f389d0c3af96d1cd49e50ca1e74221bee5e4e9", "parents": [ "d0aa6740323e48d4b3743dc8fcd5c0ff552f86d1" ], "author": { "name": "Lewis Hyatt", "email": "lhyatt@gmail.com", "time": "Thu Aug 13 21:43:19 2026 -0400" }, "committer": { "name": "Lewis Hyatt", "email": "lhyatt@gcc.gnu.org", "time": "Thu Aug 13 21:44:43 2026 -0400" }, "message": "lto: testsuite: Fix incr-link tests on wrapped targets\n\nFor targets that use a gluefile wrapper object, the extra object should not\nbe included in the link for the new LTO incr-link mode.\n\ngcc/testsuite/ChangeLog:\n\n\t* lib/lto.exp (lto-link-and-maybe-run): Unset gluefile for the\n\tincremental link step, since the wrapper is not needed there and\n\tdoes not contain LTO sections.\n" }, { "commit": "d0aa6740323e48d4b3743dc8fcd5c0ff552f86d1", "tree": "341efbbc0aa3847d19285ed80b148642f8664d05", "parents": [ "090baea02d768ff884d1b326d6bf7d57cfcc1231" ], "author": { "name": "H.J. Lu", "email": "hjl.tools@gmail.com", "time": "Fri Aug 07 16:21:54 2026 +0800" }, "committer": { "name": "H.J. Lu", "email": "hjl.tools@gmail.com", "time": "Fri Aug 14 08:40:10 2026 +0800" }, "message": "x86: Update cpuid.h to pass leaf to __get_cpuid_max\n\ncommit 44cc8e5718efd0cc1ef57c68052dbe33b047f158\nAuthor: Ewan \u003cewanhai-oc@zhaoxin.com\u003e\nDate: Tue Mar 17 16:12:15 2026 +0800\n\n i386: Fix __get_cpuid() and __get_cpuid_count() for Centaur/Zhaoxin CPUID ra\nnge\n\ncaused many regressions, like\n\nFAIL: gcc.dg/vect/vect-100.c scan-tree-dump-not optimized \"Invalid sum\"\n\non Linux/x86-64 with -m32. The commit above changed __get_cpuid_count\nwhich is used by check_vect in tree-vect.h. When GCC tried to vectorize\ncheck_vect, it outputted\n\n__attribute__((noinline))\nvoid check_vect ()\n{\n...\n;; Invalid sum of incoming counts 966367640 (estimated locally, freq 0.9000),\nshould be 719407024 (estimated locally, freq 0.6700)\n\nwhich failed\n\n/* { dg-final { scan-tree-dump-not \"Invalid sum\" \"optimized\" } } */\n\nChange __get_cpuid and __get_cpuid_count to pass the leaf argument\ndirectly to __get_cpuid_max and apply 0xC0000000 mask before passing\nit to CPUID.\n\n\tPR testsuite/126697\n\t* config/i386/cpuid.h (__get_cpuid_max): Rename the first\n\targument to __leaf and apply 0xC0000000 mask before passing\n\tit to CPUID.\n\t(__get_cpuid): Pass __leaf to __get_cpuid_max.\n\t(__get_cpuid_count): Likewise.\n\nSigned-off-by: H.J. Lu \u003chjl.tools@gmail.com\u003e\n" }, { "commit": "090baea02d768ff884d1b326d6bf7d57cfcc1231", "tree": "cd7dadc0a6629474eea8cb37e1652ac0b8de512f", "parents": [ "70bbb9a8a65a73502bace18f31ade8c0ac5f1f68" ], "author": { "name": "Jeff Law", "email": "jeffrey.law@oss.qualcomm.com", "time": "Thu Aug 13 18:34:48 2026 -0600" }, "committer": { "name": "Jeff Law", "email": "jeffrey.law@oss.qualcomm.com", "time": "Thu Aug 13 18:34:48 2026 -0600" }, "message": "[PR rtl-optimization/126426] Handle vector mode uses conservatively in ext-dce\n\nSo ext-dce isn\u0027t terribly vector aware, it mostly tries to stay out of the way\nand stay conservatively correct when vector modes are encountered.\n\nWhen that code was added in 2023/2024 it goofed a very important case that has\nnow reared its ugly head.\n\nConsider a use of V2HI. What bits are live as a result of such a use? Right\nnow we record 0xffff as the bits potentially live. But that\u0027s badly wrong. We\nhave 2 HI objects, so there\u0027s actually 32 bits of live data, so 0xffffffff.\n\nWith the bits live being incorrect we can incorrectly remove an extension\nbecause we think the bits are never read. That\u0027s precisely what happens in\nthis PR.\n\nNot much motivation was given for using GET_MODE_INNER rather than GET_MODE\nother than it works better for vector/complex. I should have caught this when\nit was introduced.\n\nFor a destination, GET_MODE_INNER is safe. The worst case is we\u0027ll fail to\nmark bits as dead which in turn will inhibit optimization. For a source\noperand it\u0027s a completely different story. By failing to mark some bits as\nlive we can (as this pr showed) erroneously remove an extension.\n\nWhile reviewing all the uses of GET_MODE_INNER, I\u0027ve become convinced the\nvector handling in carry_backpropagate is broken. If it\u0027s going to support\nvector, it needs to do what it\u0027s doing now with the GET_MODE_INNER stuff which\ngives us liveness of an element, then broadcast the liveness state across all\nthe elements of the vector. It seems like it should be possible to support\nthis case, but having not seen anything even close to it in practice, I\u0027m\npunting it for now and returning a conservatively correct state when presented\nwith vector modes in carry_backpropagate.\n\nThis has been bootstrapped and regression tested on riscv64, x86_64, aarch64,\nalpha, hppa and others. It\u0027s also been tested without regressions on the\nvarious *-elf targets. Pushing to the trunk.\n\n\tPR rtl-optimization/126426\n\ngcc/\n\t* ext-dce.cc (carry_backpropagate): Return a conservatively\n\tcorrect mask when presented with vector modes.\n\t(ext_dce_process_uses): Don\u0027t use GET_MODE_INNER, we need to\n\tknow the full extent of the bits for vector and complex modes.\n\ngcc/testsuite\n\t* gcc.target/riscv/pr126426.c: New test.\n" }, { "commit": "70bbb9a8a65a73502bace18f31ade8c0ac5f1f68", "tree": "288b5f666317d331813578b8ddf5ea1a31643668", "parents": [ "864a0748f3e9fdd1505a26002bd348a95ed3076a" ], "author": { "name": "GCC Administrator", "email": "gccadmin@gcc.gnu.org", "time": "Fri Aug 14 00:16:31 2026 +0000" }, "committer": { "name": "GCC Administrator", "email": "gccadmin@gcc.gnu.org", "time": "Fri Aug 14 00:16:31 2026 +0000" }, "message": "Daily bump." }, { "commit": "864a0748f3e9fdd1505a26002bd348a95ed3076a", "tree": "ed4801b79a5a82f8caa6c94f432b9dc520abca29", "parents": [ "e34e364a520f67d371c2aba43828ec1c50aef71f" ], "author": { "name": "Kael Andrew Alonzo Franco", "email": "kaelfandrew@gmail.com", "time": "Wed Aug 12 20:03:39 2026 -0400" }, "committer": { "name": "Kael Andrew Alonzo Franco", "email": "kaelfandrew@gmail.com", "time": "Thu Aug 13 19:40:44 2026 -0400" }, "message": "tree-optimization: Remove dead code in tree-ssa-forwprop.cc. [PR120582]\n\nThis is dead since COND_EXPR is always a SSA_NAME or a constant.\n\nBootstrapped and regtested on x86_64-pc-linux-gnu.\n\n\tPR tree-optimization/120582\n\ngcc/ChangeLog:\n\n\t* tree-ssa-forwprop.cc (simplify_builtin_call): Remove dead code.\n\nSigned-off-by: Kael Andrew Franco \u003ckaelfandrew@gmail.com\u003e\n" }, { "commit": "e34e364a520f67d371c2aba43828ec1c50aef71f", "tree": "db551a797de117bd9b77f4f7350379713ff848be", "parents": [ "e407d1bc83ae75d8a4ca0b0c04dcf0d843ce1d7a" ], "author": { "name": "Kael Andrew Alonzo Franco", "email": "kaelfandrew@gmail.com", "time": "Wed Aug 12 20:11:25 2026 -0400" }, "committer": { "name": "Kael Andrew Alonzo Franco", "email": "kaelfandrew@gmail.com", "time": "Thu Aug 13 19:40:36 2026 -0400" }, "message": "sanitizer: Remove dead code in sancov.cc. [PR120581]\n\nThis is dead since COND_EXPR is always a SSA_NAME or a constant.\n\nBootstrapped and regtested on x86_64-pc-linux-gnu.\n\n\tPR sanitizer/120581\n\ngcc/ChangeLog:\n\n\t* sancov.cc (sancov_pass): Remove dead code.\n\nSigned-off-by: Kael Andrew Franco \u003ckaelfandrew@gmail.com\u003e\n" }, { "commit": "e407d1bc83ae75d8a4ca0b0c04dcf0d843ce1d7a", "tree": "2a836867bf6d6f6001d7dd926780167094adec19", "parents": [ "a03b3ab4b0a6a446fe9a1d7e6e82967a8dd3edcf" ], "author": { "name": "Kael Andrew Alonzo Franco", "email": "kaelfandrew@gmail.com", "time": "Wed Aug 12 19:55:10 2026 -0400" }, "committer": { "name": "Kael Andrew Alonzo Franco", "email": "kaelfandrew@gmail.com", "time": "Thu Aug 13 19:40:27 2026 -0400" }, "message": "tree-optimization: Remove dead code in gimple-ssa-nonnull-compare.cc. [PR120580]\n\nThis is dead since COND_EXPR is always a SSA_NAME or a constant.\n\nBootstrapped and regtested on x86_64-pc-linux-gnu.\n\n\tPR tree-optimization/120580\n\ngcc/ChangeLog:\n\n\t* gimple-ssa-nonnull-compare.cc (do_warn_nonnull_compare):\n\tRemove dead code.\n\nSigned-off-by: Kael Andrew Franco \u003ckaelfandrew@gmail.com\u003e\n" }, { "commit": "a03b3ab4b0a6a446fe9a1d7e6e82967a8dd3edcf", "tree": "b4d6e0685be3d1cb1c644ed998a538dd6dac4e5a", "parents": [ "7f549ea2b47a709e9966ce608b92a44f3d2c2353" ], "author": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Thu Aug 13 18:07:25 2026 -0400" }, "committer": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Thu Aug 13 18:07:25 2026 -0400" }, "message": "c++/modules: ICE with GMF variable later defined inline [PR126783]\n\nHere transfer_defining_module (added in r16-5213) assumes that if\na redeclaration has DECL_LANG_SPECIFIC allocated, then so must the\noriginal declaration, but this isn\u0027t true for q below. Instead we\nshould call retrofit_lang_decl to allocate DECL_LANG_SPECIFIC as\nneeded; other parts of duplicate_decls do the same.\n\n\tPR c++/126783\n\ngcc/cp/ChangeLog:\n\n\t* module.cc (transfer_defining_module): Call retrofit_lang_decl\n\tinstead of assuming the old declaration already has\n\tDECL_LANG_SPECIFIC allocated.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/modules/gmf-6.C: New test.\n\nReviewed-by: Jason Merrill \u003cjason@redhat.com\u003e\n" }, { "commit": "7f549ea2b47a709e9966ce608b92a44f3d2c2353", "tree": "41dda82866fb2ce9588cdb91bb6d0c71a5eb7671", "parents": [ "3ecb59ac017be96590653ca16cb106c68580a15f" ], "author": { "name": "Kael Andrew Alonzo Franco", "email": "kaelfandrew@gmail.com", "time": "Wed Aug 12 20:40:24 2026 -0400" }, "committer": { "name": "Kael Andrew Alonzo Franco", "email": "kaelfandrew@gmail.com", "time": "Thu Aug 13 14:56:30 2026 -0400" }, "message": "tree-optimization: Remove dead code in gimple.cc. [PR120579]\n\nThis is dead since COND_EXPR is always a SSA_NAME or a constant.\n\nBootstrapped and regtested on x86_64-pc-linux-gnu.\n\n\tPR tree-optimization/120579\n\ngcc/ChangeLog:\n\n\t* gimple.cc (gimple_could_trap_p_1): Remove dead code.\n\nSigned-off-by: Kael Andrew Franco \u003ckaelfandrew@gmail.com\u003e\n" }, { "commit": "3ecb59ac017be96590653ca16cb106c68580a15f", "tree": "ce24cc28fa026000561814b157255e0b03aa1a5d", "parents": [ "3e43b55eb8fb520b6ed161697249fcef6699d11b" ], "author": { "name": "Kael Andrew Alonzo Franco", "email": "kaelfandrew@gmail.com", "time": "Wed Aug 12 19:49:54 2026 -0400" }, "committer": { "name": "Kael Andrew Alonzo Franco", "email": "kaelfandrew@gmail.com", "time": "Thu Aug 13 14:53:43 2026 -0400" }, "message": "tree-optimization: Remove dead code in tree-ssa-math-opts.cc. [PR120477]\n\nThis is dead since COND_EXPR is always a SSA_NAME or a constant.\n\nBootstrapped and regtested on x86_64-pc-linux-gnu.\n\n\tPR tree-optimization/120477\n\ngcc/ChangeLog:\n\n\t* tree-ssa-math-opts.cc (arith_overflow_check_p): Remove dead code.\n\nSigned-off-by: Kael Andrew Franco \u003ckaelfandrew@gmail.com\u003e\n" }, { "commit": "3e43b55eb8fb520b6ed161697249fcef6699d11b", "tree": "8e763a191be3bfa2920520f18e2c1d199a0ba464", "parents": [ "6cda72b8bd646c32a691ae1424387da259f61edc" ], "author": { "name": "Aldy Hernandez", "email": "aldy@quesejoda.com", "time": "Thu Aug 13 10:28:51 2026 +0000" }, "committer": { "name": "Aldy Hernandez", "email": "aldy@quesejoda.com", "time": "Thu Aug 13 20:32:04 2026 +0200" }, "message": "backwards threader: handle SSA names occurring in abnormal PHIs\n\nThe backward threader refuses to look at any SSA name occurring in an\nabnormal PHI, but DOM\u0027s threader does, at least for PHIs where the\npath taken does not include an abnormal edge. For example:\n\n x_5(ab) \u003d PHI \u003c45(5), y_8(ab)\u003e\n ...\n if (x_5 \u003d\u003d 45)\n\nIf we\u0027re threading a path coming in from BB5, it\u0027s perfectly valid to\nthread this path, even if x_5 itself is AB.\n\nWith gimple_range_ssa_p no longer rejecting these names, the path\nsolver handles them as is: a path never includes abnormal edges, so an\nabnormal PHI still resolves to its argument on the path\u0027s incoming\nedge. Drop the last discovery restriction in the backward threader.\nOnly normal predecessor edges are ever walked, so no abnormal edge is\nduplicated.\n\nThis also enables threading computed gotos whose destination occurs\nin an abnormal PHI, which happens when the goto block is itself one\nof the goto\u0027s targets.\n\nTested on ppc64le Linux.\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/126103\n\t* tree-ssa-threadbackward.cc (back_threader::find_paths_to_names):\n\tFollow abnormal PHIs.\n\ngcc/testsuite/ChangeLog:\n\n\tPR tree-optimization/126103\n\t* gcc.dg/tree-ssa/ssa-thread-abnormal-phi-1.c: New test.\n\t* gcc.dg/tree-ssa/ssa-thread-abnormal-phi-2.c: New test.\n\t* gcc.dg/tree-ssa/backthread-computed-goto-2.c: New test.\n" }, { "commit": "6cda72b8bd646c32a691ae1424387da259f61edc", "tree": "9b148fc821573162df8a44caeb4f5c88981c3e2e", "parents": [ "6294f1d9e7536e5ffcde09d1528c918d63abfef5" ], "author": { "name": "Aldy Hernandez", "email": "aldy@quesejoda.com", "time": "Thu Aug 13 07:00:26 2026 +0000" }, "committer": { "name": "Aldy Hernandez", "email": "aldy@quesejoda.com", "time": "Thu Aug 13 20:32:04 2026 +0200" }, "message": "range: remove the abnormal-PHI restriction from gimple_range_ssa_p\n\nThe ranger has refused to look at SSA names occurring in abnormal\nPHIs since r12-4443-g93ac832f1846e4, but there is no reason range\nanalysis cannot handle them. The abnormal marker is a constraint on\ntransformations, not on analysis: no copy can be inserted on an\nabnormal edge, so the incoming value and the PHI result must\ncoalesce. Analysis learns nothing from conditions on abnormal edges\n(there are none), but PHI and copy semantics hold like anywhere else.\n\nTested on ppc64le Linux.\n\ngcc/ChangeLog:\n\n\t* gimple-range-fold.h (gimple_range_ssa_p): Remove the\n\tSSA_NAME_OCCURS_IN_ABNORMAL_PHI check.\n\t* gimple-range-path.cc (path_range_query::ssa_range_in_phi):\n\tAssert the incoming path edge is not abnormal.\n" }, { "commit": "6294f1d9e7536e5ffcde09d1528c918d63abfef5", "tree": "c750f5d6499f2b2aa55fb7836b3dd2c70d021851", "parents": [ "ea9ca5b61117e57899e848def9124ea9f40aca49" ], "author": { "name": "Jim Lin", "email": "jim@andestech.com", "time": "Thu Aug 13 11:46:58 2026 -0600" }, "committer": { "name": "Jeff Law", "email": "jeffrey.law@oss.qualcomm.com", "time": "Thu Aug 13 11:48:20 2026 -0600" }, "message": "Re: [PATCH] RISC-V: Don\u0027t emit a separate multilib for the default march/mabi\n\nSkip a multilib only when it is exactly equivalent to the default: it\nshares the default march and mabi and carries no other distinguishing\noption (such as mcmodel). A multilib that matches the default march/mabi\nbut differs in another option is kept.\n\nThis fixes a broken Ada build. When configured with\n--with-multilib-list\u003dlp64d, the lp64d multilib is the default but was\nstill emitted as a separate multilib, so MULTISUBDIR became /lib64/lp64d\ninstead of empty.\n\ngcc/ChangeLog:\n\n\t* common/config/riscv/riscv-common.cc\n\t(riscv_multi_lib_info_t::parse): Skip a multilib that is exactly\n\tequivalent to the default march/mabi.\n\nSigned-off-by: Jim Lin \u003cjim@andestech.com\u003e\n" }, { "commit": "ea9ca5b61117e57899e848def9124ea9f40aca49", "tree": "08a04c0a777bca157d9cb35ab170128fe1c3d741", "parents": [ "2bfe853b3b1703216a32a48d2bc61363140c6aea" ], "author": { "name": "Andrea Pinski", "email": "andrew.pinski@oss.qualcomm.com", "time": "Thu Aug 13 09:53:50 2026 -0700" }, "committer": { "name": "Andrea Pinski", "email": "andrew.pinski@oss.qualcomm.com", "time": "Thu Aug 13 09:56:12 2026 -0700" }, "message": "testsuite: Add a returns_twice testcase for PR126815 [PR126815]\n\nThis adds a returns_twice testcase that shows the ICE (already fixed)\nand show that adding a stmt before the call does not work either.\n\nPushed as obvious after a quick test on x86_64-linux-gnu to make sure it passes.\n\n\tPR tree-optimization/126815\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/torture/returns-twice-1.c: New test.\n\nSigned-off-by: Andrea Pinski \u003candrew.pinski@oss.qualcomm.com\u003e\n" }, { "commit": "2bfe853b3b1703216a32a48d2bc61363140c6aea", "tree": "581bf13c66966c66bfaae5d274a6f6c79c3c80eb", "parents": [ "67ec3f5215298dd7f3177ed16c10c84392db8bb6" ], "author": { "name": "Peter Bergner", "email": "bergner@tenstorrent.com", "time": "Wed Aug 12 17:53:53 2026 +0000" }, "committer": { "name": "Peter Bergner", "email": "bergner@gcc.gnu.org", "time": "Thu Aug 13 15:48:58 2026 +0000" }, "message": "RISC-V: Add Ascalon XG cpu support\n\nThis adds support for the global version of Ascalon X (tt-ascalon-xg)\nto the list of known cores. The difference between Ascalon X \u0026 XG is XG\ndoes not have the zvkng extension and it has reduced vector FP64 throughput.\n\n2026-08-12 Peter Bergner \u003cbergner@tenstorrent.com\u003e\n\ngcc/\n\t* config/riscv/riscv-cores.def (RISCV_TUNE): Add tt-ascalon-xg.\n\t(RISCV_CORE): Likewise.\n\t* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):\n\tAdd tt_ascalon_xg.\n\t* config/riscv/riscv.md (tune): Likewise.\n\t* config/riscv/tt-ascalon-d8.md (asc-xg-fp64-vec0, asc-xg-fp64-vec1):\n\tNew define_cpu_unit.\n\t(tt_ascalon_xg_fp64_vec): New define_reservation.\n\t(tt_ascalon_d8_int_load, tt_ascalon_d8_alu, tt_ascalon_d8_sfb,\n\ttt_ascalon_d8_branch, tt_ascalon_d8_float_move, tt_ascalon_d8_fcvt,\n\ttt_ascalon_d8_fcmp, tt_ascalon_d8_imul, tt_ascalon_d8_idiv,\n\ttt_ascalon_d8_fadd, tt_ascalon_d8_mul, tt_ascalon_d8_float_fma,\n\ttt_ascalon_d8_float_div_half, tt_ascalon_d8_float_div_single,\n\ttt_ascalon_d8_float_div_double, tt_ascalon_d8_popcount,\n\ttt_ascalon_d8_vec_load, tt_ascalon_d8_vec_store,\n\ttt_ascalon_d8_vec_load_strided, tt_ascalon_d8_vec_store_strided,\n\ttt_ascalon_d8_vec_load_indexed, tt_ascalon_d8_vec_store_indexed,\n\ttt_ascalon_d8_vec_loadstore_seg, tt_ascalon_d8_vec_alu_1,\n\ttt_ascalon_d8_vec_alu_2, tt_ascalon_d8_vec_alu_3,\n\ttt_ascalon_d8_vec_alu_4, tt_ascalon_d8_vec_imul, tt_ascalon_d8_vec_pop,\n\ttt_ascalon_d8_vec_crypto_aes, tt_ascalon_d8_vec_crypto_sha,\n\ttt_ascalon_d8_vec_perm_1, tt_ascalon_d8_vec_perm_3,\n\ttt_ascalon_d8_vec_perm_4, tt_ascalon_d8_vec_reduction,\n\ttt_ascalon_d8_vec_ordered_reduction, tt_ascalon_d8_vec_idiv_byte,\n\ttt_ascalon_d8_vec_idiv_half, tt_ascalon_d8_vec_idiv_single,\n\ttt_ascalon_d8_vec_idiv_double, tt_ascalon_d8_vec_float_divsqrt_half,\n\ttt_ascalon_d8_vec_float_divsqrt_single,\n\ttt_ascalon_d8_vec_float_divsqrt_double, tt_ascalon_d8_vec_mask,\n\ttt_ascalon_d8_vec_vesetvl, tt_ascalon_d8_vec_setrm,\n\ttt_ascalon_d8_vec_readlen, tt_ascalon_d8_vec_unknown):\n\tUse tt_ascalon_xg.\n\t(tt_ascalon_d8_vec_fcmp, tt_ascalon_d8_vec_fadd,\n\ttt_ascalon_d8_vec_fmul): Disable vector instructions that produce FP64\n\toutput values when tuning for tt_ascalon_xg.\n\t(tt_ascalon_xg_fp64_vec_insns): New define_insn_reservation.\n\t* doc/riscv-mcpu.texi: Regenerate.\n\t* doc/riscv-mtune.texi: Likewise.\n\nSigned-off-by: Peter Bergner \u003cbergner@tenstorrent.com\u003e\n" }, { "commit": "67ec3f5215298dd7f3177ed16c10c84392db8bb6", "tree": "ef313044a453af1151a5c47bbc8d0d72963b5d32", "parents": [ "194c8f2bc612df9f6ef1472d6279328c0b4e603e" ], "author": { "name": "Roger Sayle", "email": "roger@nextmovesoftware.com", "time": "Thu Aug 13 16:55:40 2026 +0200" }, "committer": { "name": "Roger Sayle", "email": "roger@nextmovesoftware.com", "time": "Thu Aug 13 16:57:49 2026 +0200" }, "message": "PR rtl-optimization/126315: Failure of gcc.target/arm/pr42879.c on armv7-a.\n\nMy recent patch related to PR tree-optimization/123236\ntriggers the testsuite failure of gcc.target/arm/pr42879.c\nwhich is a missed optimization on ARM with -mthumb where we\nnow fail to emit the (shorter) lsls instruction.\n\nI believe this change simply exposes an underlying problem/wart\nin combine related to WORD_REGISTER_OPERATIONS, that has been\npresent in the compiler for decades.\n\nMy opinion is that on WORD_REGISTER_OPERATIONS targets, this\ntransformation in combine can result in some very dubious RTL\n(containing a paradoxical SUBREG of an AND binary operator).\nAs a result, thumb.md (reasonably) fails to match:\n\nTrying 11 -\u003e 12:\n 11: r102:SI\u003dr98:QI#0\u00260x1\n REG_DEAD r98:QI\n 12: cc:CC\u003dcmp(r102:SI,0)\n REG_DEAD r102:SI\nFailed to match this instruction:\n(set (reg:CC 80 cc)\n (compare:CC (subreg:SI (and:QI (reg:QI 98 [ *p_6(D) ])\n (const_int 1 [0x1])) 0)\n (const_int 0 [0])))\n\nOne approach might be for WORD_REGISTER_OPERATIONS targets to\nmatch this poorly defined pseudo-canonical RTL. Should the\ncompare assume the paradoxical SUBREG is zero extended, sign\nextended or junk? Clearly the results of the comparison do\ndepend upon the high bits.\n\nFortunately, simply disabling the offending transformation fixes\nthis issue, with combine proposing very reasonable RTL, which is\nalready matched by ARM\u0027s thumb.md:\n\nTrying 11 -\u003e 12:\n 11: r102:SI\u003dr98:QI#0\u00260x1\n REG_DEAD r98:QI\n 12: cc:CC\u003dcmp(r102:SI,0)\n REG_DEAD r102:SI\nSuccessfully matched this instruction:\n(set (reg:CC_NZ 80 cc)\n (compare:CC_NZ (zero_extract:SI (subreg:SI (reg:QI 98 [ *p_6(D) ]) 0)\n (const_int 1 [0x1])\n (const_int 0 [0]))\n (const_int 0 [0])))\nSuccessfully matched this instruction:\n(set (pc)\n (if_then_else (ne (reg:CC_NZ 80 cc)\n (const_int 0 [0]))\n (label_ref 18)\n (pc)))\nallowing combination of insns 11 and 12\noriginal costs 4 + 4 \u003d 24\nreplacement cost 20\ndeferring deletion of insn with uid \u003d 11.\nmodifying other_insn 13: pc\u003d{(cc:CC_NZ!\u003d0)?L18:pc}\n REG_DEAD cc:CC\n REG_BR_PROB 548896825\ndeferring rescan insn with uid \u003d 13.\nmodifying insn i3 12: cc:CC_NZ\u003dcmp(zero_extract(r98:QI#0,0x1,0),0)\n REG_DEAD r98:QI\ndeferring rescan insn with uid \u003d 12.\n\n2026-08-13 Roger Sayle \u003croger@nextmovesoftware.com\u003e\n\ngcc/ChangeLog\n\tPR rtl-optimization/126315\n\t* combine.cc (simplify_comparison) \u003ccase AND\u003e: Delete\n\ttransformation that changed (AND (SUBREG x) C) into the\n\tnon-canonical (SUBREG (AND x C)).\n" }, { "commit": "194c8f2bc612df9f6ef1472d6279328c0b4e603e", "tree": "71a9813b7a288debbf70e8de877d1ff687bc764b", "parents": [ "4c136e1d333bc4cf142adbb17d644d5ded5afe63" ], "author": { "name": "Tomasz Kamiński", "email": "tkaminsk@redhat.com", "time": "Thu Aug 13 14:38:29 2026 +0200" }, "committer": { "name": "Tomasz Kamiński", "email": "tkaminsk@redhat.com", "time": "Thu Aug 13 14:42:48 2026 +0200" }, "message": "libstdc++: Remove trailing whitespace in src/c++23/std.cc.in.\n\nlibstdc++-v3/ChangeLog:\n\n\t* src/c++23/std.cc.in: Remove tailing whitespace\n\tafter #endif.\n" }, { "commit": "4c136e1d333bc4cf142adbb17d644d5ded5afe63", "tree": "4043025882ebd2c356c8d21132004f5a299ce2ff", "parents": [ "6481867ae01355a2fbf296561daee9af0376f736" ], "author": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Thu Aug 13 09:24:09 2026 +0200" }, "committer": { "name": "Richard Biener", "email": "rguenth@gcc.gnu.org", "time": "Thu Aug 13 14:15:39 2026 +0200" }, "message": "Add vector integer support to double-conversion patterns\n\nThe following expands the double-conversion match patterns to also\ncover integer vectors (it already supports float vectors), adding\nrequired guards for supportability. I have simplified\nsupportable_convert_operation by eliding the useless output code\nargument (it\u0027s always the same as the input code).\n\n\t* match.pd ((convert (convert @0))): Allow integer vector\n\ttypes, unify {inside,intrer,final}_vec, guard patterns that\n\tare not correct for vectors and those that are with\n\tchecks the resulting conversion is supported by the target.\n\t* optabs-tree.h (supportable_convert_operation): Remove\n\tuseless last argument.\n\t* optabs-tree.cc (supportable_convert_operation): Likewise.\n\t(supportable_half_widening_operation): Adjust.\n\t* tree-vect-stmts.cc (vectorizable_conversion): Likewise.\n\t(supportable_indirect_convert_operation): Likewise.\n\t* tree-vect-generic.cc (expand_vector_conversion): Likewise.\n\t* tree-vect-data-refs.cc (vect_gather_scatter_fn_p): Likewise.\n\t* tree-ssa-forwprop.cc (simplify_vector_constructor): Likewise.\n\nCo-Authored-By: H.J. Lu \u003chjl.tools@gmail.com\u003e\n" }, { "commit": "6481867ae01355a2fbf296561daee9af0376f736", "tree": "b77dafdfcd540e7b846e48f21c29f310c5a40162", "parents": [ "4af34d33c9e006eb8a142fe09910e8d25c188a48" ], "author": { "name": "Josef Melcr", "email": "josef.melcr@suse.com", "time": "Tue Aug 11 10:35:16 2026 +0200" }, "committer": { "name": "Josef Melcr", "email": "josef.melcr@suse.com", "time": "Thu Aug 13 11:56:15 2026 +0200" }, "message": "ipa: Implement a summary for callback edges\n\nCurrently in trunk, every edge contains a 16 bit field called\ncallback_id, which is used to link callback edges to their attributes,\nfrom which all additional information is calculated as is needed.\n\nThis patch adds a new summary struct for callback edges, called\ncallback_info. It allows us to remove callback_id from the main class\nand aggregate all relevant information, without having to recalculate it\nevery single time.\n\ngcc/ChangeLog:\n\n\t* Makefile.in: Add callback-info.o to OBJS.\n\t* attr-callback.cc (callback_fetch_attr_by_edge): Use fn_idx\n\tfrom the summary.\n\t(callback_get_arg_mapping): Replaced by\n\tcallback_get_arg_mapping_from_attr and the summary field.\n\t(callback_get_arg_mapping_from_attr): New function, parses the\n\tattr and returns the computed argument mapping.\n\t(callback_fetch_fn_position): Delete, obsoleted by the summary.\n\t(callback_edge_useful_p): Check for the redirected flag in the\n\tsummary instead of cgraph_node fields.\n\t* attr-callback.h (enum callback_position): Add comment.\n\t(enum arg_mapping_constants): New enum, defines the identifier\n\tfor -1 in the arg_mapping vector.\n\t(callback_get_arg_mapping): Delete.\n\t(callback_fetch_fn_position): Delete.\n\t(callback_get_arg_mapping_from_attr): Add decl.\n\t* cgraph.cc (symbol_table::create_edge): Remove callback_id initializer.\n\t(cgraph_edge::make_callback): Initialize the callback_info\n\tsummary, add necessary arguments.\n\t(cgraph_edge::redirect_callee): Set the redirected flag when\n\tredirecting a callback edge.\n\t(cgraph_edge::redirect_call_stmt_to_callee): Use the summary.\n\t(cgraph_node::verify_node): Remove callback_id checks.\n\t(cgraph_cc_finalize): Free the summaries.\n\t* cgraph.h: Remove callback_id from cgraph_edge, adjust decl of\n\tcgraph_edge::make_callback.\n\t* cgraphclones.cc (cgraph_edge::clone): Remove callback_id.\n\t* ipa-cp.cc (ipcp_driver): Initialize the summary sum.\n\t* ipa-prop.cc (ipa_compute_jump_functions_for_edge): Remove\n\tcallback_id, adjust call to make_callback, use the summary.\n\t(ipa_analyze_node): Initialize the summary sum.\n\t(ipa_register_cgraph_hooks): Likewise.\n\t* lto-cgraph.cc (lto_output_edge): Remove callback_id, stream\n\tout the summary.\n\t(output_symtab): Initialize the summary sum.\n\t(input_edge): Remove callback_id, stream in the summary.\n\t(input_cgraph_1): Initialize the summary sum.\n\t* callback-info.cc: New file.\n\t* callback-info.h: New file.\n\nSigned-off-by: Josef Melcr \u003cjosef.melcr@suse.com\u003e\n" }, { "commit": "4af34d33c9e006eb8a142fe09910e8d25c188a48", "tree": "435c03a60821a7f1b20821a3ae6b3b9497ea345f", "parents": [ "26ba7ae2c5dafa759314faa5ed6dfa3b3a159368" ], "author": { "name": "Tomasz Kamiński", "email": "tkaminsk@redhat.com", "time": "Thu Aug 13 07:54:44 2026 +0200" }, "committer": { "name": "Tomasz Kamiński", "email": "tkaminsk@redhat.com", "time": "Thu Aug 13 11:34:24 2026 +0200" }, "message": "libstdc++: Ignore filesystem::canonical errors for /etc/localtime [PR125467]\n\nWhile the errors from realpath (and readlink before r17-2048-gcc195f7b11a406)\nare ignored (str is left empty), the filesystem::canonical path thrown\nexception in such situation. This patch ignores the error consistently,\nby using error_code overload of filesystem::canonical.\n\nThe !ec check before str assignment is not necessary, as standard requires\nthat filesystem::canonical returns empty path, but I think it helps\nreadability.\n\nlibstdc++-v3/ChangeLog:\n\n\tPR libstdc++/125467\n\t* src/c++20/tzdb.cc (tzdb::current_zone): Use error_code overload\n\tof filesystem::canonical to ignore errors.\n\nReviewed-by: Jonathan Wakely \u003cjwakely@redhat.com\u003e\nSigned-off-by: Tomasz Kamiński \u003ctkaminsk@redhat.com\u003e\n" }, { "commit": "26ba7ae2c5dafa759314faa5ed6dfa3b3a159368", "tree": "2696734f77517f46a33f755c2666ceaa3fd75509", "parents": [ "fbc358491eac26f6680d738c59c9ce62564988f6" ], "author": { "name": "Mikael Morin", "email": "mikael@gcc.gnu.org", "time": "Thu Aug 13 11:03:52 2026 +0200" }, "committer": { "name": "Mikael Morin", "email": "mikael@gcc.gnu.org", "time": "Thu Aug 13 11:03:52 2026 +0200" }, "message": "fortran: Fix element size in CO_BROADCAST implementation [PR126799]\n\nSimilarly to the previous element size fix touching the shared memory\nimplementation of collective subroutines, use the element length field\ninstead of the span field of the input descriptor as element size in the\nCO_BROADCAST shared memory implementation. Contrary to the collective\nsubroutine case, using the span could only cause extra memory usage here,\nwithout any more harm, and there is no testcase with any observable\nbehaviour change.\n\n\tPR fortran/126799\n\nlibgfortran/ChangeLog:\n\n\t* caf/shmem/collective_subroutine.c (collsub_broadcast_array): Use\n\tthe element length field instead of the span field as element size.\n" }, { "commit": "fbc358491eac26f6680d738c59c9ce62564988f6", "tree": "3b332859a07de9191701112651135a084ac64828", "parents": [ "424bd64ef45e001c425c18652d0dca1d7ad98928" ], "author": { "name": "Mikael Morin", "email": "mikael@gcc.gnu.org", "time": "Thu Aug 13 09:40:14 2026 +0200" }, "committer": { "name": "Mikael Morin", "email": "mikael@gcc.gnu.org", "time": "Thu Aug 13 09:40:14 2026 +0200" }, "message": "fortran: Fix element size in collective subroutines implementation [PR126799]\n\nThe shared memory implementation of collective subroutines uses the array\ndescriptor span as element size. This gives a bigger value than the true\nsize in some cases, as demonstrated in the testcase with a pointer pointing\nto an array subreference. The bigger size estimate doesn\u0027t only cause\nover allocation of memory. As the packing and unpacking functions don\u0027t\nhave the same problem, they initialize and copy back only a part of the\nallocated buffer, and their element indexing in the buffer doesn\u0027t match\nthat of the collective subroutine, causing wrong values to be produced.\n\n\tPR fortran/126799\n\nlibgfortran/ChangeLog:\n\n\t* caf/shmem/collective_subroutine.c (collsub_reduce_array): Use\n\tthe element length field instead of the span field as element size.\n\ngcc/testsuite/ChangeLog:\n\n\t* gfortran.dg/coarray/collectives_5.f90: New test.\n" }, { "commit": "424bd64ef45e001c425c18652d0dca1d7ad98928", "tree": "ffc96c6f6c09465eee5eac5dae8016fe2da22ac9", "parents": [ "1374c269134364e5241051c45363e1b0c381f550" ], "author": { "name": "Andrea Pinski", "email": "andrew.pinski@oss.qualcomm.com", "time": "Thu Aug 13 00:06:57 2026 -0700" }, "committer": { "name": "Andrea Pinski", "email": "andrew.pinski@oss.qualcomm.com", "time": "Thu Aug 13 00:11:24 2026 -0700" }, "message": "dce: Fix check for no_delete for removing the lhs of a call\n\nI only noticed after doing a bootstrap/test and pushing the\npatch that I messed up the conditional. There was no failure\nthere so I suspect it was not being tested and most likely\ndoes not run into the issue of why no_delete was added either.\n\nPushed the fix after a build.\n\ngcc/ChangeLog:\n\n\t* tree-ssa-dce.cc (simple_dce_from_worklist): Fix conditional\n\tfor no_delete with a call.\n\nSigned-off-by: Andrea Pinski \u003candrew.pinski@oss.qualcomm.com\u003e\n" }, { "commit": "1374c269134364e5241051c45363e1b0c381f550", "tree": "72b2e1e8e51b38ff2a432662fd8aa61b6f5f3968", "parents": [ "ad3f5b0855ef5f3efd6b0a13c29f98cdbf598eb7" ], "author": { "name": "Andrea Pinski", "email": "andrew.pinski@oss.qualcomm.com", "time": "Wed Aug 12 17:58:22 2026 -0700" }, "committer": { "name": "Andrea Pinski", "email": "andrew.pinski@oss.qualcomm.com", "time": "Thu Aug 13 00:00:37 2026 -0700" }, "message": "dce: Don\u0027t remove lhs for calls for no_delete case [PR126815]\n\nr17-3204-ge02ce3b8c4574c added a no_delete to simple_dce_from_worklist.\nWith the no_delete option, for calls where the lhs would be removed,\nsimple_dce_from_worklist would insert an assignment after the call.\nBut with exceptions the call is required to be last stmt in the basic block.\nNote inserting before the call would not work either because of requirements\nof returns twice functions need to be the first stmt of the basic block (\nsee gimple_verify_flow_info).\nSo the fix is instead just not removing the lhs for no_delete case.\n\nPushed as obvious after a bootstrap/test on x86_64-linux-gnu.\n\n\tPR tree-optimization/126815\n\ngcc/ChangeLog:\n\n\t* tree-ssa-dce.cc (simple_dce_from_worklist): Just don\u0027t\n\tremove the lhs for no_delete case rather than adding a\n\tnew stmt.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/torture/pr126815-1.C: New test.\n\nSigned-off-by: Andrea Pinski \u003candrew.pinski@oss.qualcomm.com\u003e\n" }, { "commit": "ad3f5b0855ef5f3efd6b0a13c29f98cdbf598eb7", "tree": "82dd2b026eec5c5c0b0c9268234543762b17929d", "parents": [ "542d7eaf767057fbd224d44dbc1772dea3e41891" ], "author": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Aug 05 12:22:59 2026 +0200" }, "committer": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Thu Aug 13 08:21:34 2026 +0200" }, "message": "libcpp: add an AArch64 SVE2 search_line_fast\n\nThe AArch64 helper that finds the next \u0027\\n\u0027, \u0027\\r\u0027, \u0027\\\\\u0027 or \u0027?\u0027 scans a\nfixed 16 bytes per iteration and spends more than half of its per-call\ncost outside the loop, turning a vector comparison into a byte index.\n\nSVE2 does the whole thing in far fewer instructions and, being\nvector-length agnostic, keeps scaling on implementations wider than\n128 bits. Every 128-bit segment of the needle vector holds the four\ncharacters, so a single MATCH reports set membership for the whole\nvector, and MATCH sets the condition flags directly, so the loop branch\nneeds no reduction. BRKB and INCP then convert the result predicate\nstraight into a pointer increment.\n\n Neon, 16 bytes per iteration: SVE2, svcntb () bytes per iteration:\n\n ldr q1, [x1, #16]! ld1b z0.b, p0/z, [x0]\n cmeq v2.16b, v1.16b, v3.16b match p1.b, p0/z, z0.b, z1.b\n cmeq v4.16b, v1.16b, v5.16b b.none .Lloop\n cmeq v0.16b, v1.16b, v6.16b\n cmeq v1.16b, v1.16b, v7.16b and to extract the index:\n orr v2.16b, v2.16b, v0.16b\n orr v4.16b, v4.16b, v1.16b brkb p0.b, p0/z, p1.b\n orr v2.16b, v2.16b, v4.16b incp x0, p0.b\n addp d0, v2.2d\n fmov x0, d0\n cbz x0, .Lloop\n\n and v2.16b, v2.16b, v16.16b\n uaddlp v2.8h, v2.16b\n ushl v2.8h, v2.8h, v17.8h\n addv h2, v2.8h\n fmov w0, s2\n rbit w0, w0\n clz w0, w0\n\nThe loop needs neither alignment nor a page-crossing test. Full-vector\nloads run while S is at or below END rounded down to a vector boundary,\nso they may extend a little past *END into the tail padding; a\npredicated vector covers any remainder. It relies on *END being one of\nthe four characters, which _cpp_convert_input guarantees.\n\nSVE2 is not in the AArch64 baseline, so the helper is compiled with a\n+sve2 target attribute and selected by getauxval at start-up. The\nselection is a predictable branch rather than a function pointer, so the\nNeon helper is still inlined into _cpp_clean_line and hosts without SVE2\nkeep exactly the code they have today. When the configure probe fails\nthe SVE2 path is not compiled at all.\n\nMeasured on two 128-bit SVE2 implementations, Grace and Vera.\nA standalone harness driving the helper the way\n_cpp_clean_line does, over 41 MB of GCC and libstdc++ sources, is 89%\nfaster than the Neon helper on both, and 91 to 95% faster over libstdc++\nheaders alone.\n\nCorrectness was checked with a harness that places the buffer against a\nPROT_NONE guard page, with the SVE tail padding after the terminating\nnewline, and sweeps every start alignment and match distance for all\nfour characters and all 256 byte values, run natively and under\nemulation at vector lengths of 128, 256, 512, 1024 and 2048 bits, both\nlittle-endian and big-endian.\n\nBootstrapped and tested on aarch64-none-linux-gnu.\n\nlibcpp/ChangeLog:\n\n\t* configure.ac: Test whether the AArch64 SVE2 lexer can be built.\n\t* config.in: Regenerate.\n\t* configure: Regenerate.\n\t* internal.h (CPP_BUFFER_PADDING): Increase to 256 for SVE2.\n\t* lex.cc (search_line_fast): Rename AArch64 Neon version to...\n\t(search_line_neon): ...this.\n\t(search_line_sve2): New function.\n\t(lexer_has_sve2): New variable.\n\t(init_vectorized_lexer): New function.\n\t(search_line_fast): New function, dispatching between the two.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/cpp/vector-scan-align.c: New test.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n" }, { "commit": "542d7eaf767057fbd224d44dbc1772dea3e41891", "tree": "fc87238c5169dab6639e0e706e9a7c30d0b26869", "parents": [ "c5d147d7370fb36834c9348c5d3bab229d89fb3e" ], "author": { "name": "Rohith Kapelli", "email": "kapellirohith@gmail.com", "time": "Wed Aug 12 22:05:23 2026 -0600" }, "committer": { "name": "Jeff Law", "email": "jeffrey.law@oss.qualcomm.com", "time": "Wed Aug 12 22:05:23 2026 -0600" }, "message": "[PATCH v3] simplify-rtx: widen the memory attributes when folding \"c ? a : a\" [PR125683]\n\nsimplify_ternary_operation folds IF_THEN_ELSE (cond, a, a) to a using\nrtx_equal_p, which ignores the memory attributes. Two loads from the\nsame address into the same register are rtx_equal_p even when they have\nincompatible alias sets, so the fold returned one arm\u0027s MEM and the\nresult inherited just that arm\u0027s (too narrow) alias set.\n\nnoce_try_ifelse_collapse builds exactly such an IF_THEN_ELSE from the two\nsides of\n\n long f (int a, void *cc, long *d)\n {\n long long c;\n *d \u003d 0;\n if (a) c \u003d *(long *) cc; else c \u003d *(long long *) cc;\n *d \u003d 1;\n return c;\n }\n\nso ce1 replaced the two loads with a single long long load; a later pass,\nseeing that a long long load does not alias the long store to *d, deleted\nthe \"dead\" *d \u003d 0, and with cc \u003d\u003d d the function returned a stale value.\n\nRather than dropping the fold when the attributes differ, keep it and\nreturn a reference that only claims what both operands guarantee, in the\nspirit of merge_memattrs: alias set 0 when the sets differ, MEM_EXPR and\noffset cleared when they disagree, and the minimum alignment. The\noperands can be shared, so the attributes are set on a shallow copy\nrather than in place.\n\nMEM_READONLY_P, MEM_NOTRAP_P and MEM_POINTER each assert something about\nthe reference, so the copy keeps them only when both operands do. They\nare rtx flag bits rather than MEM_ATTRS fields, so shallow_copy_rtx takes\nthem from the first operand and they have to be cleared by hand; the\nequal-attributes early exit tests them too, so a disagreement in a flag\nalone still goes through the copy. merge_memattrs already drops the\nfirst two this way when it commons two references, so this only follows\nit; it does not look at MEM_POINTER, which is treated the same way here\nbecause it is an assertion about the loaded value in just the same\nsense.\n\nUnlike merge_memattrs, which fixes up two references that both remain in\nthe instruction stream, this returns a single reference standing in for\neither arm, so the size is kept only when both agree instead of taking\nthe larger one. BLKmode is left alone because there MEM_ATTRS describes\nthe size of the access itself. Volatility is not merged: it constrains\nwhen the access happens rather than describing the memory, so it can be\nneither weakened (that would lose a required access) nor strengthened as\nmerge_memattrs does (that would add a volatile access on the arm which\ndid not have one, there being a single access left for either arm), and\nthe fold is declined instead. Address spaces need no check: rtx_equal_p\nalready fails for MEMs in different address spaces.\n\nSeveral tree passes can factor the two loads with a conservative type\nbefore RTL and so hide this: PRE and code hoisting on the release\nbranches, and the phi-opt load factoring (PR125557) on trunk. The test\ndisables them so the if-conversion path is exercised on every affected\nversion. It is a live wrong-code at -O2 on the 13/14/15/16 branches --\ngcc-13 miscompiles the reduced case at plain -O2 with no such flags at\nall.\n\n---\n\nChanges since v2: MEM_READONLY_P, MEM_NOTRAP_P and MEM_POINTER are now\ndropped when the two arms disagree. They are rtx flag bits rather than\nMEM_ATTRS fields, so shallow_copy_rtx brings them across from the first\noperand and they have to be cleared by hand; they are cleared on the\nfresh MEM the fold already builds, not on either operand, which can be\nshared. The equal-attributes early exit tests them too, so a\ndisagreement in a flag alone still goes through the copy.\n\nmerge_memattrs already clears the first two this way, so MEM_POINTER is\nthe one flag this adds to that treatment.\n\nNew test gcc.dg/rtl/aarch64/pr125683-flags.c builds the disagreement\ndirectly, because it cannot be produced from C source: MEM_READONLY_P\nand MEM_NOTRAP_P are derived from the base object, which two loads from\nthe same address share. It is gated to aarch64-*-* because rtl.exp\ncollects tests recursively, so every __RTL test has to gate itself, and\n__RTL tests hard-code target register names.\n\nTesting, on aarch64-unknown-linux-gnu: patched and unpatched bootstrapped\nfrom clean trees in the same environment, both stage2 \u003d\u003d stage3.\nComparing every result line across gcc, g++, libstdc++, libgomp, libitm\nand libatomic -- normalising the build directory, which g++.dg/modules\nembeds in test names -- the two runs are identical except for this\npatch\u0027s own tests. One apparent transition,\ng++.dg/tsan/pthread_cond_clockwait.C at -O0, is a flaky execution test:\nre-run idle eight times per compiler it passed 2/8 unpatched and 1/8\npatched. The runtime test is revert-sensitive: the unpatched compiler\naborts on it, the patched one exits 0. The patch applies cleanly to\ntrunk and to the gcc-16, gcc-15, gcc-14 and gcc-13 branches.\n\n\tPR rtl-optimization/125683\n\ngcc/ChangeLog:\n\n\t* simplify-rtx.cc (simplify_context::simplify_ternary_operation):\n\tWhen folding an IF_THEN_ELSE of two equal MEM operands with\n\tdifferent memory attributes, return a copy whose attributes are\n\twidened to what both operands allow.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/pr125683.c: New test.\n\t* gcc.dg/rtl/aarch64/pr125683-flags.c: New test.\n\nSigned-off-by: Rohith Kapelli \u003ckapellirohith@gmail.com\u003e\n" }, { "commit": "c5d147d7370fb36834c9348c5d3bab229d89fb3e", "tree": "b7b92ea5c389d7b0b2f049590777a61e3dcf40c5", "parents": [ "4f75092d25c099363892d03cb50b1142fb20bdcc" ], "author": { "name": "Pan Li", "email": "pan2.li@intel.com", "time": "Wed Aug 12 10:42:29 2026 +0800" }, "committer": { "name": "Pan Li", "email": "pan2.li@intel.com", "time": "Thu Aug 13 09:25:40 2026 +0800" }, "message": "RISC-V: Add more test cases for vwmacc[u].vv\n\nFor csrr not asm check when enable overlap enabled.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/base/pr112431-49.c: New test.\n\t* gcc.target/riscv/rvv/base/pr112431-50.c: New test.\n\nSigned-off-by: Pan Li \u003cpan2.li@intel.com\u003e\n" }, { "commit": "4f75092d25c099363892d03cb50b1142fb20bdcc", "tree": "2f07ddeb0ea96a7511fbdf365bb29a50b1dad3fe", "parents": [ "55afdf36b7a2acd881c93485ce2af6d1cf006e18" ], "author": { "name": "Pan Li", "email": "pan2.li@intel.com", "time": "Wed Aug 12 10:42:29 2026 +0800" }, "committer": { "name": "Pan Li", "email": "pan2.li@intel.com", "time": "Thu Aug 13 09:25:40 2026 +0800" }, "message": "RISC-V: Add test cases for vwmaccu.vv reg overlap\n\nAdd test cases for register group overlap, please\nnote it is not overlap as much as possible.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u16-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u16-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u16-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u16-mf2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u16-mf4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u32-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u32-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u32-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u32-mf2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u8-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u8-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u8-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u8-mf2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u8-mf4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vv-u8-mf8.c: New test.\n\nSigned-off-by: Pan Li \u003cpan2.li@intel.com\u003e\n" }, { "commit": "55afdf36b7a2acd881c93485ce2af6d1cf006e18", "tree": "5bbbf1c4b8f82873ecefd1dfbcbc19c19caddb3f", "parents": [ "2be327c50de607ab0d8c1a2295160313c7edf6db" ], "author": { "name": "Pan Li", "email": "pan2.li@intel.com", "time": "Wed Aug 12 10:42:17 2026 +0800" }, "committer": { "name": "Pan Li", "email": "pan2.li@intel.com", "time": "Thu Aug 13 09:25:39 2026 +0800" }, "message": "RISC-V: Add test cases for vwmacc.vv reg overlap\n\nAdd test cases for register group overlap, please\nnote it is not overlap as much as possible.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h:\n\tAdd test helper macros.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i16-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i16-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i16-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i16-mf2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i16-mf4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i32-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i32-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i32-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i32-mf2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i8-m1.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i8-m2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i8-m4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i8-mf2.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i8-mf4.c: New test.\n\t* gcc.target/riscv/rvv/autovec/group_overlap/vwmacc_vv-i8-mf8.c: New test.\n\nSigned-off-by: Pan Li \u003cpan2.li@intel.com\u003e\n" }, { "commit": "2be327c50de607ab0d8c1a2295160313c7edf6db", "tree": "6ec7fa5efb82844d0187bcdd8366dbd01a1de7fb", "parents": [ "ee9c991d1567aa6677b21abab7d01e9fdf86b5a9" ], "author": { "name": "Pan Li", "email": "pan2.li@intel.com", "time": "Fri Aug 07 21:10:56 2026 +0800" }, "committer": { "name": "Pan Li", "email": "pan2.li@intel.com", "time": "Thu Aug 13 09:25:39 2026 +0800" }, "message": "RISC-V: Allow RVV register overlap for vwmacc[u].vv\n\nLike vw{add,sub,mul}[u].vv, allow the rvv register overlap for\nthe dual widen ternary vv insn vwmacc.vv and vwmaccu.vv.\n\ngcc/ChangeLog:\n\n\t* config/riscv/vector.md: Leverage Wvr constraint.\n\nSigned-off-by: Pan Li \u003cpan2.li@intel.com\u003e\n" }, { "commit": "ee9c991d1567aa6677b21abab7d01e9fdf86b5a9", "tree": "de45235c6315f27f9db68c587d20d5ee56acb782", "parents": [ "15acadc08ca83c2993fe96bcf185079587ba95bb" ], "author": { "name": "GCC Administrator", "email": "gccadmin@gcc.gnu.org", "time": "Thu Aug 13 00:16:40 2026 +0000" }, "committer": { "name": "GCC Administrator", "email": "gccadmin@gcc.gnu.org", "time": "Thu Aug 13 00:16:40 2026 +0000" }, "message": "Daily bump." }, { "commit": "15acadc08ca83c2993fe96bcf185079587ba95bb", "tree": "49f7ca0591c659f4def15d155dc3f15aabedbe67", "parents": [ "1c03a15e0979c76a33276cbf498379084896cd06" ], "author": { "name": "Robert Dubner", "email": "rdubner@symas.com", "time": "Wed Aug 12 18:38:20 2026 -0400" }, "committer": { "name": "Robert Dubner", "email": "rdubner@symas.com", "time": "Wed Aug 12 19:12:39 2026 -0400" }, "message": "cobol: Refactor the use of cbl_char_t for big-endian architecture.\n\nOne of the features of GCOBOL is that it can function with the\n-fexec-charset set to ASCII, EBCDIC, UTF16LE, UTF16BE, UTF32LE, or\nUTF32BE. When I recently started work on getting the compiler to work\nproperly on a big-endian IBM System Z, I realized I had built in a lot\nof little-endian assumptions that got in the way of handling big- and\nlittle-endian character sets on a big-endian machine.\n\nThese changes eliminate some of those assumptions, so that the 32-bit\ncbl_char_t means the same thing on both big- and little-endian\narchitectures.\n\ngcc/cobol/ChangeLog:\n\n\t* genapi.cc (get_level_88_domain): Expanded comment.\n\t(create_and_call): Handle CALL USING BY VALUE ZERO.\n\t* structs.cc: Updated comment.\n\t* util.cc: Prevent segfault when the procedures_t(size_t)\n\tconstructor is invoked with exactly 512 symbols.\n\nlibgcobol/ChangeLog:\n\n\t* charmaps.h (ascii_at): New define for \u0027@\u0027,\n\t(charmap_load_unaligned): Eliminate.\n\t(charmap_store_unaligned): Eliminate.\n\t(store_uint16): Eliminate.\n\t(store_uint32): Eliminate.\n\t(class charmap_t): Make m_ascii_sign_bit, ::getch, ::putch, and\n\t::memset behave for big-endian architectures.\n\t* gfileio.cc (write_a_char): Behave properly on big-endian\n\tarchitectures.\n\t(sequential_file_write): Likewise.\n\t(line_sequential_file_read_sbc): Likewise.\n\t(line_sequential_file_read): Likewise.\n\t* libgcobol.cc (edited_to_binary): Simplified.\n\t(int128_to_field): Proper big-endian behavior.\n\t(uber_compare): Proper big-endian behavior, simplified ABI.\n\t(__gg__dirty_to_binary): Simplified.\n\t(compare_strings): Use new uber_compare call.\n\t(__gg__compare_2): Likewise.\n" }, { "commit": "1c03a15e0979c76a33276cbf498379084896cd06", "tree": "ff8b2d90b562c8067789d637064237dd0369c595", "parents": [ "15d60983ca428032c4a92fe9f195faa918ba5095" ], "author": { "name": "Iain Sandoe", "email": "iain@sandoe.co.uk", "time": "Tue Aug 11 11:58:18 2026 +0100" }, "committer": { "name": "Iain Sandoe", "email": "iain@sandoe.co.uk", "time": "Wed Aug 12 23:05:50 2026 +0100" }, "message": "Darwin: Amend linker-visibility of strings [PR126723].\n\nThere seems to be quite some variability in the cases that clang makes\nstring constant labels linker-visible, however the most conservative\ncase is \"all of them\" which appears to be the strategy for aarch64.\nWe dadopt this here, although there is some slight loss of efficiency\nfor x86_64.\n\n\tPR target/126723\n\ngcc/ChangeLog:\n\n\t* config/darwin.cc (darwin_encode_section_info): Make all\n\tstring constant labels linker-visible. Likewise const\n\tsection anchors.\n\nSigned-off-by: Iain Sandoe \u003ciain@sandoe.co.uk\u003e\n" }, { "commit": "15d60983ca428032c4a92fe9f195faa918ba5095", "tree": "dfeed3ded3126ff73049af014c3c5edd4670ce4f", "parents": [ "2aeac7315ee65fd3829fddd4835bb549c69dbda9" ], "author": { "name": "Iain Sandoe", "email": "iain@sandoe.co.uk", "time": "Thu Oct 26 10:57:43 2023 +0100" }, "committer": { "name": "Iain Sandoe", "email": "iain@sandoe.co.uk", "time": "Wed Aug 12 23:05:01 2026 +0100" }, "message": "testsuite, aarch64: Gate CFI/CFA tests on the cfi effective target.\n\nTargets might not support .cfi_ instructions, gate tests that require\nthese using the existing target supports.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/dwarf-cfa-reg.c: Require cfi instructions.\n\t* gcc.target/aarch64/stack-check-cfa-1.c: Likewise.\n\t* gcc.target/aarch64/stack-check-cfa-2.c: Likewise.\n\t* gcc.target/aarch64/stack-check-cfa-3.c: Likewise.\n\nSigned-off-by: Iain Sandoe \u003ciain@sandoe.co.uk\u003e\n" }, { "commit": "2aeac7315ee65fd3829fddd4835bb549c69dbda9", "tree": "2b57f3d5f4942c205b568b183024402cc432a1d0", "parents": [ "cc08be7bf549072bf3699a57d3d37222e8c1087d" ], "author": { "name": "Iain Sandoe", "email": "iain@sandoe.co.uk", "time": "Wed Jul 15 08:17:43 2026 +0100" }, "committer": { "name": "Iain Sandoe", "email": "iain@sandoe.co.uk", "time": "Wed Aug 12 23:04:42 2026 +0100" }, "message": "testsuite, aarch64: Add dg-requires for mabi\u003dilp32.\n\nNot all targets have this support, add a dg-requires for cases that need\nit. Add a target supports for it and use it.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/inline-mem-set-pr112804.c: Require\n\tmabi-ilp32 support.\n\t* gcc.target/aarch64/pr100518.c: Likewise.\n\t* gcc.target/aarch64/pr113114.c: Likewise.\n\t* gcc.target/aarch64/pr80295.c: Likewise.\n\t* gcc.target/aarch64/pr94201.c: Likewise.\n\t* gcc.target/aarch64/pr94577.c: Likewise.\n\t* gcc.target/aarch64/sve/pr108603.c: Likewise.\n\t* lib/target-supports.exp: Add target supports for mabi\u003dilp32.\n\nSigned-off-by: Iain Sandoe \u003ciain@sandoe.co.uk\u003e\n" }, { "commit": "cc08be7bf549072bf3699a57d3d37222e8c1087d", "tree": "decb11494b54de9e1d89a7d2cd51647708d5b5d1", "parents": [ "7f4f4b9fe867c07b597412629c7b33636db4a066" ], "author": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Wed Aug 12 15:58:39 2026 -0400" }, "committer": { "name": "Patrick Palka", "email": "ppalka@redhat.com", "time": "Wed Aug 12 15:58:39 2026 -0400" }, "message": "c++: do not hash TYPENAME_TYPEs on pointers [PR124811]\n\ntypename_htab is written to a precompiled header. A hash table is\nstreamed out slot array and all: gt_pch_nx() relocates the pointers\ninside the entries but leaves every entry in the slot it happened to\noccupy. typename_hasher hashed on the addresses of the scope and the\nfullname, so the slots were chosen from addresses that ASLR randomises\nin the process writing the header, and they no longer correspond to the\nhash of anything once the header has been read back at a different\naddress.\n\nLookups then find a restored TYPENAME_TYPE only when it happens to lie\non the probe sequence of the slot the new hash points at, so most miss\nand build a duplicate, and which ones miss depends on the layout the\nwriting process had. That makes a compile using a PCH differ from the\nsame compile without one, and differ from itself between runs: the\nduplicates consume DECL_UIDs, every later DECL_UID shifts, and\nvar-tracking hashes on DECL_UID, so .debug_loclists comes out different.\n\nHash on TYPE_UID instead, which the header preserves, and use\niterative_hash_template_arg to properly hash fullname which can be an\narbitrary TEMPLATE_ID_EXPR. (It\u0027s important to hash the fullname instead\nof just the name for sake of the PR c++/65328 compile-time-hog testcase.)\n\n\tPR c++/124811\n\ngcc/cp/ChangeLog:\n\n\t* decl.cc (typename_hasher::hash): Instead of pointer hashing,\n\thash TYPE_HASH of context and use iterative_hash_template_arg\n\tto hash fullname.\n\nCo-authored-by: Bernhard M. Wiedemann \u003cbwiedemann@suse.de\u003e\nReviewed-by: Jason Merrill \u003cjason@redhat.com\u003e\n" }, { "commit": "7f4f4b9fe867c07b597412629c7b33636db4a066", "tree": "fd351b84d3c48eded04775e3fa3f3984ee098fd6", "parents": [ "f296bb38423fb786f20d213f9f87bf2c7ce14b63" ], "author": { "name": "Aldy Hernandez", "email": "aldy@quesejoda.com", "time": "Tue Aug 04 10:03:39 2026 +0000" }, "committer": { "name": "Aldy Hernandez", "email": "aldy@quesejoda.com", "time": "Wed Aug 12 21:29:52 2026 +0200" }, "message": "[frange] Convert range_operator::fold_range to sub-ranges.\n\nFold each pair of operand sub-ranges through rv_fold and union the\nresults, which keeps the gaps between sub-ranges instead of folding\nthe [lower, upper] hull. When the operands are known equal (x op x)\nfold the diagonal instead, folding each sub-range against itself.\nThis follows irange\u0027s fold_range.\n\nTested on ppc64le Linux: regstrap, LAPACK. Shrinks 6 of 3631 LAPACK\nasm TUs, none larger.\n\ngcc/ChangeLog:\n\n\t* range-op-float.cc (range_operator::fold_range): Fold each pair\n\tof sub-ranges, or the diagonal when the operands are equal.\n\t(range_op_float_tests): New test.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/tree-ssa/vrp-float-subrange-1.c: New test.\n" }, { "commit": "f296bb38423fb786f20d213f9f87bf2c7ce14b63", "tree": "3b8e7284531f679b380544dc92c2dba8d1b6e746", "parents": [ "21d8d36e3e7b4255d9a62a85109d47cc67de0461" ], "author": { "name": "Uros Bizjak", "email": "ubizjak@gmail.com", "time": "Wed Aug 12 21:13:15 2026 +0200" }, "committer": { "name": "Uros Bizjak", "email": "ubizjak@gmail.com", "time": "Wed Aug 12 21:21:02 2026 +0200" }, "message": "i386: Fix some minor issues with BT patterns\n\nRelax register constraint on operand 1 of *bt\u003cmode\u003e from \"q\" to \"r\"\nso it is no longer restricted to the legacy byte-addressable register\nclass. Also remove the unneeded \"r,m\" constraints on operand 0\nof *bt\u003cSWI48:mode\u003e_mask pre-reload splitter, keeping only the\nnonimmediate_operand predicate.\n\ngcc/ChangeLog:\n\n\t* config/i386/i386.md (*bt\u003cmode\u003e): Change operand 1 constraint\n\tfrom \"q\u003cS\u003e,\u003cS\u003e\" to \"r\u003cS\u003e,\u003cS\u003e\".\n\t(*bt\u003cSWI48:mode\u003e_mask): Remove constraints from operand 0.\n" }, { "commit": "21d8d36e3e7b4255d9a62a85109d47cc67de0461", "tree": "d971b4dd0d9925febe46a8e7596d769293f7d31f", "parents": [ "5ad734dea0161726c74fb2c42a07f0fe7f8e1e02" ], "author": { "name": "Georg-Johann Lay", "email": "avr@gjlay.de", "time": "Wed Aug 12 20:48:14 2026 +0200" }, "committer": { "name": "Georg-Johann Lay", "email": "avr@gjlay.de", "time": "Wed Aug 12 20:48:14 2026 +0200" }, "message": "AVR: Tidy round insns for 1- and 2-byte modes.\n\ngcc/\n\t* config/avr/avr-fixed.md (*round\u003cmode\u003e3.libgcc_split)\n\t(*round\u003cmode\u003e3.libgcc): Use the ALL12QA mode iterator instead\n\tof ALL1Q and ALL2QA separately.\n" }, { "commit": "5ad734dea0161726c74fb2c42a07f0fe7f8e1e02", "tree": "a93a5337ec809b20e51af47af9c692e57e54b1ee", "parents": [ "6bf1714eae8f686338cbc2f4e2cd7b828a13254b" ], "author": { "name": "Georg-Johann Lay", "email": "avr@gjlay.de", "time": "Wed Aug 12 20:26:37 2026 +0200" }, "committer": { "name": "Georg-Johann Lay", "email": "avr@gjlay.de", "time": "Wed Aug 12 20:33:45 2026 +0200" }, "message": "AVR: Support saturating fixed-point shifts.\n\nThis patch adds support for saturated shift left of all the\nfixed-point modes -- except for the Reduced Core where no\n64-bit shifts are added.\n\navr-fixed.md adds insns to model the reduced register foot\nprints of all the shifts up to 4 bytes.\n\ngcc/\n\t* config/avr/avr-fixed.md (ALL12QA): New mode iterator.\n\t(sat_ashl): New code iterator.\n\t(usashluqq3, ssashlqq3, usashluhq3, ssashlhq3, usashluha3)\n\t(ssashlha3, usashlusq3, ssashlsq3, usashlusa3, ssashlsa3)\n\t(*usashluqq3, *ssashlqq3, *usashluhq3, *ssashlhq3)\n\t(*usashluha3, *ssashlha3, *usashlusq3, *ssashlsq3, *usashlusa3)\n\t(*ssashlsa3): New insns.\n\t* config/avr/avr.md (code_stdname): Also map ss_ashift, us_ashift.\nlibgcc/\n\t* config/avr/t-avr (LIB1ASMFUNCS): Add _usshift_1, _usshift_2,\n\t_usshift_4, _ssshift_1, _ssshift_2, _ssshift_4.\n\t(FUNCS_notiny): Add _usshift_8, _ssshift_8.\n\t(LIB2FUNCS_EXCLUDE): Add all the default libgcc saturated shifts.\n\t* config/avr/lib1funcs-fixed.S: Support saturated ashl for\n\tall fixed-point modes.\ngcc/testsuite/\n\t* gcc.target/avr/fx.h: New file.\n\t* gcc.target/avr/sat-shift-s.c: New test.\n\t* gcc.target/avr/sat-shift-u.c: New test.\n" }, { "commit": "6bf1714eae8f686338cbc2f4e2cd7b828a13254b", "tree": "734eeb4be949b2bcdd0a04acba97730d7a934f66", "parents": [ "610f1166538ad2e637c913be78b074100270cc5c" ], "author": { "name": "Gerald Pfeifer", "email": "gerald@pfeifer.com", "time": "Wed Aug 12 20:18:24 2026 +0200" }, "committer": { "name": "Gerald Pfeifer", "email": "gerald@pfeifer.com", "time": "Wed Aug 12 20:18:24 2026 +0200" }, "message": "doc: Update link to RISC-V Vector Intrinsics specification\n\ngcc:\n\t* doc/extend.texi (RISC-V Vector Intrinsics): Update link to\n\tspecification.\n" }, { "commit": "610f1166538ad2e637c913be78b074100270cc5c", "tree": "0cfd70f541b2493c5b5497685aaecdb6165502e4", "parents": [ "c491043565ac1ea0003326a69cbfaf5b922eb142" ], "author": { "name": "Andrea Pinski", "email": "andrew.pinski@oss.qualcomm.com", "time": "Mon Jul 27 20:11:33 2026 -0700" }, "committer": { "name": "Andrea Pinski", "email": "andrew.pinski@oss.qualcomm.com", "time": "Wed Aug 12 10:02:20 2026 -0700" }, "message": "match: Fix recent pattern for signed integer overflow dealing with - [PR126418]\n\nA recent match patterns were added that introduce signed integer overflow where\nthere was none before. `cmp + (-cmp ^ x)` has no signed integer overflow when\nx is INT_MIN when cmp is 0. This gets translated into cmp ? -x : x.\nBut this has now introduced an signed integer overflow for INT_MIN.\nThe fix is to use unsigned type for the negative.\n\nBootstrapped and tested on x86_64-linux-gnu.\n\nChanges since v1:\n* v2: Remove the abs patterns since a signed integer overflow would have happened anyways.\n\n\tPR tree-optimization/126418\n\ngcc/ChangeLog:\n\n\t* match.pd (`(A ^ -cmp) + cmp`): Cast to unsigned type\n\tbefore taking the negative.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/tree-ssa/pr126418-1.c: New test.\n\nSigned-off-by: Andrea Pinski \u003candrew.pinski@oss.qualcomm.com\u003e\n" }, { "commit": "c491043565ac1ea0003326a69cbfaf5b922eb142", "tree": "16c5cd825bddc798a89d29ee3a90a38b2dc424f5", "parents": [ "019ccd080992657b08900692386b65ee4a6679fd" ], "author": { "name": "Matt Turner", "email": "mattst88@gmail.com", "time": "Wed Aug 12 10:11:59 2026 -0600" }, "committer": { "name": "Jeff Law", "email": "jeffrey.law@oss.qualcomm.com", "time": "Wed Aug 12 10:11:59 2026 -0600" }, "message": "[PATCH v2] alpha: enable gnu-indirect-function support for alpha-linux\n\nEnable __attribute__((ifunc)) for alpha*-*-linux*, which sets\nHAVE_GNU_INDIRECT_FUNCTION\u003d1 and makes targetm.has_ifunc_p() return\ntrue.\n\nNo Alpha backend changes are needed -- the generic ifunc machinery in\nvarasm.cc handles emission, and alpha/elf.h already provides the\nrequired ASM_OUTPUT_TYPE_DIRECTIVE and ASM_OUTPUT_DEF macros.\n\nRather than defaulting default_gnu_indirect_function to yes in\nconfig.gcc, this follows the riscv*-*-linux* precedent and gates the\ndefault on a toolchain feature test. A plain assembler test would not\nbe meaningful: %gnu_indirect_function is handled by generic ELF code in\ngas and has been accepted for every target for many years. The real\ndependency is on the linker emitting R_ALPHA_IRELATIVE, so the test\nassembles, links and inspects the relocations with readelf. Without it\nthe link silently succeeds while producing an ordinary R_ALPHA_JMP_SLOT.\n\nThe existing riscv test is generalized to select the expected relocation\nname per target so both share one code path. Alpha needs its own test\nsource because alpha gas reserves .set for setting assembler modes, so\nthe alias is spelled with \u0027\u003d\u0027, matching the target\u0027s ASM_OUTPUT_DEF.\n\nRuntime support additionally requires a glibc dynamic linker that\nhandles the new relocation.\n\n---\nChanges in v2:\n - Gate the default on a linker feature test instead of unconditionally\n adding alpha*-* to default_gnu_indirect_function in config.gcc, per\n Jeff\u0027s question about depending on an unreleased binutils.\n - Generalize the existing riscv*-*-linux* IRELATIVE check so both\n targets share one code path.\n\nTested by running the generated configure fragment against both an\nalpha-linux-gnu binutils with the pending IFUNC support and the stock\n2.47 release; it reports yes and no respectively. With stock 2.47 the\nassembler accepts %gnu_indirect_function and emits an STT_GNU_IFUNC\nsymbol, and the link then succeeds while dropping the relocation\nentirely, so an assembler-only test would not catch this.\n\ngcc/ChangeLog:\n\n\t* configure.ac (gcc_cv_irelative_reloc): New variable, set for\n\triscv*-*-linux* and alpha*-*-linux*. Perform the linker\n\tIRELATIVE check once, driven by it.\n\t* configure: Regenerate.\n" }, { "commit": "019ccd080992657b08900692386b65ee4a6679fd", "tree": "4eeeaf7b32778077ebb5cc761ab3d017b960face", "parents": [ "98298f05f6b110e20714987829558bb77564a10a" ], "author": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Tue Aug 04 06:46:04 2026 -0700" }, "committer": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Aug 12 17:22:27 2026 +0200" }, "message": "aarch64: use [SU]DOT for the byte to word step of a widening sum\n\nA widening sum from bytes into 64-bit elements spends two [SU]ADDLP\ngetting from bytes to words. With dot product that step is a single\n[SU]DOT against a vector of ones, which is what the byte to word expander\nalready does for a 4x reduction. Each 32-bit element then holds the sum\nof four input elements, at most 4 * 255 unsigned and within -512 to 508\nsigned, so no sum can overflow.\n\nMove the dot product step into aarch64_expand_reduc_widen_sum, so that any\nchain that passes through a byte to word step uses it. The only shape that\ngains is V2DI \u003c- V16QI, because the other shapes either do not start from\nbytes or already stop at 32-bit elements:\n\n V8HI \u003c- V16QI [SU]ADALP word elements would be too wide\n V4SI \u003c- V8HI [SU]ADALP not a byte source\n V2DI \u003c- V4SI [SU]ADALP not a byte source\n V2SI \u003c- V8QI [SU]DOT unchanged\n V4SI \u003c- V16QI [SU]DOT unchanged\n V2DI \u003c- V8HI [SU]ADDLP + [SU]ADALP not a byte source\n V2DI \u003c- V16QI [SU]DOT + [SU]ADALP new\n\nWithout dot product every shape keeps the pairwise chain.\n\nFor a sum of unsigned char into long the inner loop changes from\n\n\tldr\tq31, [x2], 16\n\tuaddlp\tv31.8h, v31.16b\n\tuaddlp\tv31.4s, v31.8h\n\tuadalp\tv30.2d, v31.4s\n\nto\n\n\tldr\tq29, [x2], 16\n\tmovi\tv31.4s, 0\n\tudot\tv31.4s, v29.16b, v27.16b\n\tuadalp\tv30.2d, v31.4s\n\nwith the vector of ones in v27 hoisted out of the loop. The instruction\ncount is unchanged but the vector work is spread better.\nA sum of unsigned char into long runs about 24% faster at\n-march\u003darmv8.2-a+dotprod, and about 20% faster with an L1 resident working\nset at -mcpu\u003dneoverse-v2, where the vectorizer unrolls the loop by four.\n\nBootstrapped and tested on aarch64-none-linux-gnu.\nOk for trunk?\nThanks,\nKyrill\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-simd.md (reduc_widen_\u003csu\u003esum\u003cmode\u003e\u003cvsi2qi\u003e3):\n\tExpand through aarch64_expand_reduc_widen_sum.\n\t* config/aarch64/aarch64.cc (aarch64_expand_reduc_widen_sum): Use\n\t[SU]DOT for a step from byte to word elements.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/widen_sum_pairwise_2.c: Cover every widening\n\tsum shape and check the dot product sequences.\n\t* gcc.target/aarch64/widen_sum_pairwise_3.c: New test.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n" }, { "commit": "98298f05f6b110e20714987829558bb77564a10a", "tree": "d014a802a1a5a5b3b807b200a6d575e00707471c", "parents": [ "d9e21f7c4d1666baec96398f07ac500d1c912a12" ], "author": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Sun Aug 02 08:04:42 2026 -0700" }, "committer": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Aug 12 17:22:13 2026 +0200" }, "message": "aarch64: use [SU]ADDLP/[SU]ADALP for widening sum reductions\n\nThe Advanced SIMD reduc_widen_[su]sum optabs only cover a single widening\nstep, expanded as a dependent \u003csu\u003eaddw + \u003csu\u003eaddw2 pair, plus a 4x form\nthat requires dot product. A reduction into an accumulator that is more\nthan twice as wide as the data therefore has to extend the input explicitly\nand then issue one widening add per half vector. Summing bytes into a\n64-bit accumulator costs fifteen SIMD operations per 16 bytes of input.\n\n[SU]ADDLP and [SU]ADALP add adjacent lane pairs into the next wider\nelement, so a chain of them expresses any power-of-two widening sum\nreduction in one operation per step. The regrouping is exact because the\nsum of two elements always fits in the doubled element width, and the\ngrouping of lanes inside a reduction accumulator is already unconstrained\nfor WIDEN_SUM_EXPR, which the existing dot product based 4x expander also\nrelies on.\n\nExpand the 2x forms as a single [SU]ADALP, add the missing V4SI \u003c- V16QI\nand V2SI \u003c- V8QI forms for !TARGET_DOTPROD, and add the V2DI \u003c- V8HI and\nV2DI \u003c- V16QI forms that no expander covered. The chains are built by\naarch64_expand_reduc_widen_sum, which halves the lane count with [SU]ADDLP\nuntil one pairwise step is left and then accumulates with [SU]ADALP. Every\nAdvanced SIMD shape is now covered, and the sequence chosen for each is\n\n V8HI \u003c- V16QI [SU]ADALP\n V4SI \u003c- V8HI [SU]ADALP\n V2DI \u003c- V4SI [SU]ADALP\n V2SI \u003c- V8QI [SU]DOT, or [SU]ADDLP + [SU]ADALP without dot product\n V4SI \u003c- V16QI [SU]DOT, or [SU]ADDLP + [SU]ADALP without dot product\n V2DI \u003c- V8HI [SU]ADDLP + [SU]ADALP\n V2DI \u003c- V16QI [SU]ADDLP + [SU]ADDLP + [SU]ADALP\n\nFor a sum of unsigned char into long the inner loop changes from\n\n\tldr\tq30, [x1], 16\n\tzip1\tv28.16b, v30.16b, v29.16b\n\tzip2\tv30.16b, v30.16b, v29.16b\n\tzip1\tv26.8h, v28.8h, v29.8h\n\tzip2\tv28.8h, v28.8h, v29.8h\n\tzip1\tv27.8h, v30.8h, v29.8h\n\tzip2\tv30.8h, v30.8h, v29.8h\n\tuaddw\tv31.2d, v31.2d, v26.2s\n\tuaddw2\tv31.2d, v31.2d, v26.4s\n\t... (six more uaddw/uaddw2)\n\nto\n\n\tldr\tq31, [x1], 16\n\tuaddlp\tv31.8h, v31.16b\n\tuaddlp\tv31.4s, v31.8h\n\tuadalp\tv30.2d, v31.4s\n\nand for a sum of int into long the saddw/saddw2 pair becomes one sadalp.\nOn a Grace core with an L1 resident working set this cuts the time of the\nbyte loop by about 88% and of the int loop by about 68%.\n\nBootstrapped and tested on aarch64-none-linux-gnu.\nOk for trunk?\nThanks,\nKyrill\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-protos.h (aarch64_expand_reduc_widen_sum):\n\tDeclare.\n\t* config/aarch64/aarch64.cc (aarch64_expand_reduc_widen_sum): New\n\tfunction.\n\t* config/aarch64/aarch64-simd.md (aarch64_\u003csu\u003eadalp\u003cmode\u003e): Rename\n\tto ...\n\t(@aarch64_\u003csu\u003eadalp\u003cmode\u003e): ... this.\n\t(reduc_widen_ssum\u003cVdblw\u003e\u003cmode\u003e3, reduc_widen_usum\u003cVdblw\u003e\u003cmode\u003e3):\n\tReplace by ...\n\t(reduc_widen_\u003csu\u003esum\u003cVdblw\u003e\u003cmode\u003e3): ... this. Expand to [SU]ADALP.\n\t(reduc_widen_ssum\u003cmode\u003e\u003cvsi2qi\u003e3, reduc_widen_usum\u003cmode\u003e\u003cvsi2qi\u003e3):\n\tReplace by ...\n\t(reduc_widen_\u003csu\u003esum\u003cmode\u003e\u003cvsi2qi\u003e3): ... this. Handle\n\t!TARGET_DOTPROD.\n\t(reduc_widen_\u003csu\u003esumv2di\u003cmode\u003e3): New expander.\n\t* config/aarch64/iterators.md (VQ_BH): New mode iterator.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/pr122069_1.c: Update expected output.\n\t* gcc.target/aarch64/pr122069_3.c: Likewise.\n\t* gcc.target/aarch64/saddw-1.c: Renamed to...\n\t* gcc.target/aarch64/sadalp-1.c: ...this. Update expected output.\n\t* gcc.target/aarch64/saddw-2.c: Renamed to...\n\t* gcc.target/aarch64/sadalp-2.c: ...this. Update expected output.\n\t* gcc.target/aarch64/uaddw-1.c: Renamed to...\n\t* gcc.target/aarch64/uadalp-1.c: ...this. Update expected output.\n\t* gcc.target/aarch64/uaddw-2.c: Renamed to...\n\t* gcc.target/aarch64/uadalp-2.c: ...this. Update expected output.\n\t* gcc.target/aarch64/uaddw-3.c: Renamed to...\n\t* gcc.target/aarch64/uadalp-3.c: ...this. Update expected output.\n\t* gcc.target/aarch64/widen_sum_pairwise_1.c: New test.\n\t* gcc.target/aarch64/widen_sum_pairwise_2.c: New test.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n" }, { "commit": "d9e21f7c4d1666baec96398f07ac500d1c912a12", "tree": "ed4a03316b06e786d07d724ffa3df60d1e46f72c", "parents": [ "2e722bc990f8a64ad80e2f6a565ef1d5f206a7e0" ], "author": { "name": "H.J. Lu", "email": "hjl.tools@gmail.com", "time": "Fri Jul 17 08:35:34 2026 +0800" }, "committer": { "name": "H.J. Lu", "email": "hjl.tools@gmail.com", "time": "Wed Aug 12 22:24:20 2026 +0800" }, "message": "x86-64: Add -m128bit-atomic\n\nWith the silicon vendor guarantees from Intel, AMD, Hygon and Zhaoxin in:\n\nhttps://gcc.gnu.org/bugzilla/show_bug.cgi?id\u003d104688\n\nmany software developers would happily use inline 128-bit atomic loads\nand stores in their programs because they only target compatible CPUs.\nAdd -m128bit-atomic to generate 128-bit atomic loads and stores to avoid\nthe overhead of calling into libatomic. Enable -m128bit-atomic in 64-bit\nmode by default if supported by the targeting processor, which is one of\nx86-64-v3 capable processors as well as AVX capable processors from Intel,\nAMD, Hygon and Zhaoxin.\n\ngcc/\n\n\tPR target/94649\n\tPR target/126293\n\t* common/config/i386/i386-cpuinfo.h (ix86_decode_cpu_info): New\n\tfunction.\n\t* config/i386/i386-options.cc\n\t(ix86_option_override_internal): Issue an error for -m128bit-atomic\n\tin 32-bit mode. Turn on -mcx16 if -m128bit-atomic is enabled.\n\tEnable -m128bit-atomic in 64-bit mode by default if supported by\n\tthe targeting processor.\n\t* config/i386/i386.h (TARGET_128BIT_ATOMIC_ENABLED): New.\n\t* config/i386/i386.opt (m128bit-atomic): New option.\n\t* config/i386/i386.opt.urls: Regenerated.\n\t* config/i386/sync.md: Update comments for 128-bit aligned vector\n\tloads and stores.\n\t(atomic_loadti): New pattern.\n\t(atomic_loadti_sse): Likewise.\n\t(atomic_storeti): Likewise.\n\t(atomic_storeti_sse): Likewise.\n\t* doc/invoke.texi: Remove __atomic Builtins reference from -mcx16.\n\tDocument -m128bit-atomic.\n\ngcc/testsuite/\n\n\tPR target/94649\n\tPR target/126293\n\t* g++.target/i386/pr94649-1.C: New test.\n\t* gcc.target/i386/pr126293-1a.c: Likewise.\n\t* gcc.target/i386/pr126293-1b.c: Likewise.\n\t* gcc.target/i386/pr126293-1c.c: Likewise.\n\t* gcc.target/i386/pr126293-1d.c: Likewise.\n\t* gcc.target/i386/pr126293-2a.c: Likewise.\n\t* gcc.target/i386/pr126293-2b.c: Likewise.\n\t* gcc.target/i386/pr126293-3a.c: Likewise.\n\t* gcc.target/i386/pr126293-3b.c: Likewise.\n\t* gcc.target/i386/pr126293-4a.c: Likewise.\n\t* gcc.target/i386/pr126293-4b.c: Likewise.\n\t* gcc.target/i386/pr126293-4c.c: Likewise.\n\t* gcc.target/i386/pr126293-4d.c: Likewise.\n\t* gcc.target/i386/pr126293-4e.c: Likewise.\n\t* gcc.target/i386/pr126293-4f.c: Likewise.\n\t* gcc.target/i386/pr126293-4g.c: Likewise.\n\t* gcc.target/i386/pr126293-4h.c: Likewise.\n\t* gcc.target/i386/pr126293-4i.c: Likewise.\n\t* gcc.target/i386/pr126293-4j.c: Likewise.\n\t* gcc.target/i386/pr126293-4k.c: Likewise.\n\t* gcc.target/i386/pr126293-4l.c: Likewise.\n\t* gcc.target/i386/pr126293-4m.c: Likewise.\n\t* gcc.target/i386/pr126293-4n.c: Likewise.\n\t* gcc.target/i386/pr126293-4o.c: Likewise.\n\t* gcc.target/i386/pr126293-4p.c: Likewise.\n\t* gcc.target/i386/pr126293-4q.c: Likewise.\n\t* gcc.target/i386/pr126293-4r.c: Likewise.\n\t* gcc.target/i386/pr126293-4s.c: Likewise.\n\t* gcc.target/i386/pr126293-5.c: Likewise.\n\t* gcc.target/i386/pr126293-6.c: Likewise.\n\t* gcc.target/i386/pr126293-7.c: Likewise.\n\t* gcc.target/i386/pr126293-8.c: Likewise.\n\t* gcc.target/i386/pr126293-9.c: Likewise.\n\t* gcc.target/i386/pr126293-10.c: Likewise.\n\t* gcc.target/i386/pr126293-11.c: Likewise.\n\t* gcc.target/i386/pr126293-12.c: Likewise.\n\t* gcc.target/i386/pr126293-13.c: Likewise.\n\t* gcc.target/i386/pr126293-14.c: Likewise.\n\t* gcc.target/i386/pr126293-15.c: Likewise.\n\t* gcc.target/i386/pr126293-16.c: Likewise.\n\t* gcc.target/i386/pr126293-17.c: Likewise.\n\nSigned-off-by: H.J. Lu \u003chjl.tools@gmail.com\u003e\n" }, { "commit": "2e722bc990f8a64ad80e2f6a565ef1d5f206a7e0", "tree": "e1130bf6ce35a3d98867ca729f4aceb45a5d6e14", "parents": [ "d9b294889b14069d6f6c5ce985f17bf8bbf34894" ], "author": { "name": "Tamar Christina", "email": "tamar.christina@arm.com", "time": "Wed Aug 12 14:16:12 2026 +0100" }, "committer": { "name": "Tamar Christina", "email": "tamar.christina@arm.com", "time": "Wed Aug 12 14:17:47 2026 +0100" }, "message": "vect: For now restrict vect_validate_multiplication_commutative to only 4 forms [PR126589]\n\nFlipping the order of the operands can end up changing the sign of the operation\nand to compensate an adjustment operation has to be inserted (i.e. * {-1,1}).\n\nThe current code in trunk cannot do this yet so backporting the change from my\ncomplex numbers branch caused it to produce incorrect code.\n\nFor now while the full changes aren\u0027t upstreamed remove the last 4 swaps.\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/126589\n\t* tree-vect-slp-patterns.cc (vect_validate_multiplication): Cleanup\n\tcomment.\n\t(vect_validate_multiplication_commutative): Remove last 4 orders.\n" }, { "commit": "d9b294889b14069d6f6c5ce985f17bf8bbf34894", "tree": "0a8b7f428de330c35802ccad7cd3f305306520b3", "parents": [ "b3275d4a1f199872dffd9df4967673722f270671" ], "author": { "name": "Tamar Christina", "email": "tamar.christina@arm.com", "time": "Wed Aug 12 14:15:43 2026 +0100" }, "committer": { "name": "Tamar Christina", "email": "tamar.christina@arm.com", "time": "Wed Aug 12 14:17:16 2026 +0100" }, "message": "vect: Support another form of COMPLEX_FMS which the testcases point out [PR126589]\n\nThis adds support for matching FMS where the reassoc has left the top level\noperation as a PLUS_MINUS.\n\ni.e. matching\n\n c.real + (a.imag * b.imag - a.real * b.real)\n c.imag - (a.real * b.imag + a.imag * b.real)\n\nwhich happens when the accumulator is not the same as the destination.\ni.e.\n\nd[i] \u003d c[i] - (a[i] * b[i])\n\nvs\n\nc[i] -\u003d a[i] * b[i]\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/126589\n\t* tree-vect-slp-patterns.cc (complex_fms_pattern::matches): Check\n\tanother form of FMS.\n\ngcc/testsuite/ChangeLog:\n\n\tPR tree-optimization/126589\n\t* gfortran.target/aarch64/pr122408_1.f90: update scans to check for FMS.\n\t* gcc.dg/vect/complex/complex-mul2.c: New test.\n\t* gcc.dg/vect/complex/fast-math-complex-mls-manual-invalid-float.c: New test.\n\t* gcc.dg/vect/complex/fast-math-complex-mls-outofplace-double.c: New test.\n\t* gcc.dg/vect/complex/fast-math-complex-mls-outofplace-float.c: New test.\n" }, { "commit": "b3275d4a1f199872dffd9df4967673722f270671", "tree": "6dcfae73db2f867c46f70d7063eaf11dd5a72a6e", "parents": [ "f49cb8938ef3ab032fe01c6a39b4baf8e4e8fa49" ], "author": { "name": "Gaius Mulley", "email": "gaiusmod2@gmail.com", "time": "Wed Aug 12 13:16:28 2026 +0100" }, "committer": { "name": "Gaius Mulley", "email": "gaiusmod2@gmail.com", "time": "Wed Aug 12 13:16:28 2026 +0100" }, "message": "PR modula2/125129: Many tests fail to link on FreeBSD\n\nNot all targets have csin[l], ccos[l] and ctan[l]. On such systems\nthe ISO libraries should be pruned thus allowing compile time failures\nfor source which explicitly requests these intrinsics rather than universally\nfail on linking. This patch introduces a new tool mktargetsrc which\nwill generate target versions of the Modula-2 libraries. The patch also\nintroduces -fdump-builtins which is used by mktargetsrc. mktargetsrc\nreplaces makeSystem and mktargetsrc improves the formatting of the\nautogenerated SYSTEM.def files.\nBootstrapped on x86_64 Debian, FreeBSD15 and ppc64le GNU/Linux.\n\ngcc/ChangeLog:\n\n\tPR modula2/125129\n\t* doc/gm2.texi (-fdump-builtins): New switch.\n\ngcc/m2/ChangeLog:\n\n\tPR modula2/125129\n\t* Make-lang.in (escape_path): New define.\n\t(GM2_FOR_TARGET_ESC): New define.\n\t(RSTSRC): Remove.\n\t(gm2-libs.texi-check): Rewrite without $(objdir).\n\t(m2/gm2-libs.rst): Remove.\n\t(gm2-ebnf.rst): Ditto.\n\t(gm2-ebnf.rst-check): Ditto.\n\t(SYSTEM-pim-texi-check): Ditto.\n\t(m2/SYSTEM-pim.rst): Ditto.\n\t(m2/SYSTEM-iso.texi): Rewrite without $(objdir).\n\t(Builtins.texi-check): Rewrite specifying $(srcdir).\n\t(m2/Builtins.rst): Remove.\n\t(MC_ARGS): Add -I$(srcdir)/m2/gm2-libs-pim-common\n\tand -I$(srcdir)/m2/mc-boot-ch.\n\t(m2/mc-boot/$(SRC_PREFIX)%.o): Add -I$(srcdir)/m2/mc-boot-ch.\n\t(m2/mc-boot-ch/$(SRC_PREFIX)%.o): Ditto.\n\t(MC_BOOT_INCLUDES): New define.\n\t(m2/gm2-libs-boot/UnixArgs.o): Add MC_BOOT_INCLUDES.\n\t(m2/gm2-libs-boot/choosetemp.o): Ditto.\n\t(m2/gm2-libs-boot/errno.o): Ditto.\n\t(m2/gm2-libs-boot/dtoa.o): Ditto.\n\t(m2/gm2-libs-boot/ldtoa.o): Ditto.\n\t(m2/gm2-libs-boot/termios.o): Ditto.\n\t(m2/gm2-libs-boot/SysExceptions.o): Ditto.\n\t(m2/gm2-libs-boot/SysStorage.o): Ditto.\n\t(m2/gm2-libs/Builtins.def): Rewrite.\n\t(m2/gm2-libs/Builtins.mod): Ditto.\n\t(m2/gm2-libs/SYSTEM.def): Ditto.\n\t(m2/gm2-libs-iso/SYSTEM.def): Ditto.\n\t(m2/gm2-libs-coroutines/SYSTEM.def): Ditto.\n\t(m2/gm2-libs/%.o): Ditto.\n\t* gm2-compiler/M2Options.def (SetDumpBuiltins): New procedure.\n\t(GetDumpBuiltins): New procedure function.\n\t* gm2-compiler/M2Options.mod (DumpBuiltinsFlag): New variable.\n\t(SetDumpBuiltins): Implement new procedure.\n\t(GetDumpBuiltins): Implement new procedure function.\n\t* gm2-compiler/M2Quads.mod (BuildComponentValue): Removed unused\n\tvariable virtpos.\n\t* gm2-gcc/m2builtins.cc (GM2_BUG_REPORT): Reformat.\n\t(ASSERT): Ditto.\n\t(ERROR): Ditto.\n\t(dump_available): New funmction.\n\t(define_builtin): Call dump_available if GetDumpBuiltins is set.\n\t(dump_builtin): New function.\n\t(m2builtins_init): Call dump_builtin.\n\t* gm2-gcc/m2options.h (M2Options_SetDumpBuiltins): New prototype.\n\t(M2Options_GetDumpBuiltins): Ditto.\n\t* gm2-lang.cc (gm2_langhook_handle_option): Add OPT_fdump_builtins\n\tcase.\n\t* gm2-libs-coroutines/SYSTEM.def: Move to...\n\t* gm2-libs-cor-common/SYSTEM.def: ...here.\n\t* gm2-libs-coroutines/SYSTEM.mod: Move to...\n\t* gm2-libs-cor-common/SYSTEM.mod: ...here.\n\t* gm2-libs-iso/ComplexMath.def: Move to...\n\t* gm2-libs-iso-common/ComplexMath.def: ...here.\n\tAdd tags.\n\t* gm2-libs-iso/ComplexMath.mod: Move to...\n\t* gm2-libs-iso-common/ComplexMath.mod: ...here.\n\tAdd tags.\n\t* gm2-libs-iso/LongComplexMath.def: Move to...\n\t* gm2-libs-iso-common/LongComplexMath.def: ...here.\n\tAdd tags.\n\t* gm2-libs-iso/LongComplexMath.mod: Move to...\n\t* gm2-libs-iso-common/LongComplexMath.mod: ...here.\n\tAdd tags.\n\t* gm2-libs-iso/SYSTEM.def: Move to...\n\t* gm2-libs-iso-common/SYSTEM.def: ...here.\n\tAdd tags.\n\t* gm2-libs-iso/SYSTEM.mod: Move to...\n\t* gm2-libs-iso-common/SYSTEM.mod: ...here.\n\tAdd tags.\n\t* gm2-libs-iso/ShortComplexMath.def: Move to...\n\t* gm2-libs-iso-common/ShortComplexMath.def: ...here.\n\tAdd tags.\n\t* gm2-libs-iso/ShortComplexMath.mod: Move to...\n\t* gm2-libs-iso-common/ShortComplexMath.mod: ...here.\n\tAdd tags.\n\t* gm2-libs/Builtins.def: Move to...\n\t* gm2-libs-pim-common/Builtins.def: ...here.\n\tAdd tags.\n\t* gm2-libs/Builtins.mod: Move to...\n\t* gm2-libs-pim-common/Builtins.mod: ...here.\n\tAdd tags.\n\t* gm2-libs/SYSTEM.def: Move to...\n\t* gm2-libs-pim-common/SYSTEM.def: ...here.\n\tAdd tags.\n\t* gm2-libs/SYSTEM.mod: Move to...\n\t* gm2-libs-pim-common/SYSTEM.mod: ...here.\n\tAdd tags.\n\t* gm2-libs/cbuiltin.def: Move to...\n\t* gm2-libs-pim-common/cbuiltin.def: ...here.\n\tAdd tags.\n\t* gm2-libs-min/SYSTEM.def: Add tags.\n\t* lang.opt (fdump-builtins): Add.\n\t* tools-src/def2doc.py: Modified to process tags.\n\t* tools-src/makeSystem: Modified to reflect new tags.\n\t* tools-src/mktargetsrc.py: New file.\n\nlibgm2/ChangeLog:\n\n\tPR modula2/125129\n\t* Makefile.am (GM2_FOR_TARGET_ESC): New define.\n\t(AM_MAKEFLAGS): Add GM2_FOR_TARGET_ESC.\n\tAdd HAVE_PYTHON_INTERPRETER.\n\t* Makefile.in: Regenerate.\n\t* aclocal.m4: Regenerate.\n\t* config.h.in: Regenerate.\n\t* configure: Regenerate.\n\t* configure.ac: Call AC_PYTHON_DEVEL.\n\tCall GCC_PICFLAG.\n\t* libm2cor/Makefile.am (libm2cor_la_M2FLAGS): Add\n\tgm2-libs-cor-common and pathname.\n\t(SYSTEM.def): Rewrite rule.\n\t(SYSTEM.mod): Copy common file.\n\t* libm2cor/Makefile.in: Regenerate.\n\t* libm2iso/Makefile.am (AM_MAKEFLAGS): Add GM2_FOR_TARGET_ESC.\n\tAdd HAVE_PYTHON_INTERPRETER.\n\t(libm2iso_la_CFLAGS): Add m2pim pathname and ../libm2pim to\n\tinclude path.\n\t* libm2log/Makefile.am: Rewrite to handle HAVE_PYTHON_INTERPRETER.\n\tFalling back to the common versions of target sources if\n\tHAVE_PYTHON_INTERPRETER is false.\n\t* libm2min/Makefile.am: Ditto.\n\t* libm2pim/Makefile.am:\tDitto.\n\t* libm2iso/Makefile.in: Regenerate.\n\t* libm2log/Makefile.in: Regenerate.\n\t* libm2min/Makefile.in: Regenerate.\n\t* libm2pim/Makefile.in: Regenerate.\n\t* ax_python_devel.m4: New file.\n\ngcc/testsuite/ChangeLog:\n\n\tPR modula2/125129\n\t* gm2/exceptions/run/pass/exceptions-run-pass.exp: Use\n\tgm2_target_compiler rather than target_compile.\n\t* lib/gm2.exp (gm2_target_compile_default): Check\n\tcheck_effective_target_pie and append -fPIE if necessary.\n\nSigned-off-by: Gaius Mulley \u003cgaiusmod2@gmail.com\u003e\n" }, { "commit": "f49cb8938ef3ab032fe01c6a39b4baf8e4e8fa49", "tree": "b26bde81dd4f7ffc35358376d6e2681a1f452393", "parents": [ "75f572322c011229794476502f52a9ae530107f8" ], "author": { "name": "Abhishek Kaushik", "email": "abhishek.kaushik@arm.com", "time": "Mon Aug 10 12:29:45 2026 +0000" }, "committer": { "name": "Abhishek Kaushik", "email": "abhishek.kaushik@arm.com", "time": "Wed Aug 12 11:46:52 2026 +0000" }, "message": "aarch64: Add SME2p3/SVE2p3 x2 narrowing right shift intrinsics\n\nThis patch adds support for the following SME2p3/SVE2p3 x2 narrowing\nright shift intrinsics:\n\n - svqrshrn_s8_s16\n - svqrshrn_u8_u16\n - svqrshrun_u8_s16\n - svqshrn_s8_s16\n - svqshrn_s16_s32\n - svqshrn_u8_u16\n - svqshrn_u16_u32\n - svqshrun_u8_s16\n - svqshrun_u16_s32\n\nBootstrapped and regression tested on aarch64-linux-gnu.\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-acle-builtins.h\n\t(TYPES_qshr_x2): New macro.\n\t(TYPES_qrshr_x2_8): Likewise.\n\t(TYPES_qshru_x2): Likewise.\n\t(TYPES_qrshrun_x2): Likewise.\n\t(DEF_SVE_TYPES_ARRAY): Add qshr_x2, qrshr_x2_8,\tqrshrun_x2\n\tand qshru_x2.\n\t* config/aarch64/aarch64-sve-builtins-sve2.cc (svqshrn): New\n\tfunction.\n\t(svqshrun): Likewise.\n\t* config/aarch64/aarch64-sve-builtins-sve2.def (svqrshrn): Add\n\tSVE2p3/SME2p3 x2 form.\n\t(svqrshrun): Likewise.\n\t(svqshrn): Add SVE2p3/SME2p3 x2 form.\n\t(svqshrun): Likewise.\n\t* config/aarch64/aarch64-sve-builtins-sve2.h (svqshrn): Declare.\n\t(svqshrun): Likewise.\n\t* config/aarch64/aarch64-sve2.md\n\t(@aarch64_sve_\u003csve_int_op\u003e\u003cmode\u003e): New define_insn.\n\t* config/aarch64/iterators.md (SVE_FULL_HIx2): New mode iterator.\n\t(UNSPEC_SQSHRN, UNSPEC_SQSHRUN, UNSPEC_UQSHRN): New unspecs.\n\t(VNARROW): Add VNx16HI mapping.\n\t(Ventype): Likewise.\n\t(SVE2_INT_SHIFT_IMM_NARROWxN): Add UNSPEC_SQSHRN,\n\tUNSPEC_SQSHRUN and UNSPEC_UQSHRN.\n\t(sve_int_op): Add sqshrn, sqshrun and uqshrn.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/sme2/acle-asm/qrshrn_s8_x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/qrshrn_u8_x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/qrshrun_u8_x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/qshrn_s16_x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/qshrn_s8_x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/qshrn_u16_x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/qshrn_u8_x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/qshrun_u16_x2.c: New test.\n\t* gcc.target/aarch64/sme2/acle-asm/qshrun_u8_x2.c: New test.\n" }, { "commit": "75f572322c011229794476502f52a9ae530107f8", "tree": "d905275bd411a265eac73d06bbc3198ffbea0fad", "parents": [ "eaca0fdd031bbed1d2ff7dd86c3adfecef1c51cc" ], "author": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Mon Aug 10 20:39:14 2026 +0200" }, "committer": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Aug 12 13:37:18 2026 +0200" }, "message": "match.pd: fold a round up spelled with inclusive or\n\nLinux spells a power-of-two round up as:\n\n ((x - 1) | (2^k - 1)) + 1\n\nFor wrapping arithmetic, this is:\n\n (x + (2^k - 1)) \u0026 -(2^k)\n\nThe latter form needs one fewer operation and exposes the zero low bits.\nApply the identity to scalar and vector integral types. Use :s on the\ninclusive-or expression so the fold does not add work when that value\nremains live.\n\n unsigned long round_up (unsigned long x)\n {\n return ((x - 1) | 4095) + 1;\n }\n\naarch64 -O2:\n\nbefore:\n\n\tround_up:\n\t\tsub\tx0, x0, #1\n\t\torr\tx0, x0, 4095\n\t\tadd\tx0, x0, 1\n\t\tret\n\nafter:\n\n\tround_up:\n\t\tadd\tx0, x0, 4095\n\t\tand\tx0, x0, -4096\n\t\tret\n\nBootstrapped and tested on aarch64-none-linux-gnu.\n\ngcc/ChangeLog:\n\n\t* match.pd (((X - 1) | C) + 1): New simplification.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/tree-ssa/round-up-ior-1.c: New test.\n\t* gcc.dg/tree-ssa/round-up-ior-2.c: Likewise.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n" }, { "commit": "eaca0fdd031bbed1d2ff7dd86c3adfecef1c51cc", "tree": "51b9f3317e04076bd7f629ae863ab1afd4272c22", "parents": [ "31fd60b80ae81191084d7999765329c132222970" ], "author": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Aug 05 14:58:44 2026 +0200" }, "committer": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Aug 12 13:33:04 2026 +0200" }, "message": "doc: describe the lane freedom of reduc_widen_[us]sum and WIDEN_SUM_EXPR\n\nThe documentation of the reduc_widen_ssum and reduc_widen_usum patterns says\nonly that operand 1 is added to operand 2, which reads as though each element\nof operand 1 has to be accumulated into the element of operand 0 at the same\nposition. Nothing says the patterns are only ever used for a reassociable\nreduction, so a port cannot tell whether it is allowed to regroup the input\nelements, for example by using a pairwise widening add.\n\nvect_recog_widen_sum_pattern only forms WIDEN_SUM_EXPR\nthrough vect_reassociating_reduction_p, which requires the statement to be a\nreduction, refuses a statement nested in the inner loop of an outer-loop\nvectorization because the order of the computation matters there, and refuses\na type that needs a fold-left reduction. The comment on the pattern already\ndescribes the idiom as producing N/2 results by summing up pairs of\nintermediate results. The accumulator is only ever consumed by a horizontal\nsum in the epilogue, so the distribution of input elements over accumulator\nelements is not observable.\n\nSpell that out in md.texi, along with the constraint that comes with it: an\nimplementation that adds elements together before they reach the element width\nof operand 0 has to widen them first so that no intermediate sum can overflow.\nNote that the widen_[us]sum names are left free for a lane preserving pattern.\n\nGive WIDEN_SUM_EXPR the same statement in tree.def. DOT_PROD_EXPR and SAD_EXPR\nare formed through vect_reassociating_reduction_p as well and read the same way,\nso add a sentence to each pointing at the WIDEN_SUM_EXPR rule.\n\ngcc/ChangeLog:\n\n\t* doc/md.texi (reduc_widen_ssum@var{n}@var{m}3)\n\t(reduc_widen_usum@var{n}@var{m}3): Document that the assignment of\n\tinput elements to accumulator elements is unconstrained, that\n\tintermediate sums must not overflow, and that the widen_[us]sum\n\tnames are reserved. Fix a typo.\n\t* tree.def (WIDEN_SUM_EXPR): Document that the assignment of elements\n\tof the first argument to elements of the second is unconstrained.\n\t(DOT_PROD_EXPR, SAD_EXPR): Note the same freedom.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n" }, { "commit": "31fd60b80ae81191084d7999765329c132222970", "tree": "06d5de590abacdd834ce0e13965374d17b3a0536", "parents": [ "adc20f13b60f90c6a55d46fc6be37dfb9f4b86a0" ], "author": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Aug 05 14:56:56 2026 +0200" }, "committer": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Aug 12 13:32:54 2026 +0200" }, "message": "optabs: rename widen_[us]sum to reduc_widen_[us]sum\n\nThe widen_ssum and widen_usum optabs are only ever used to implement the\naccumulator update of a reduction that the vectorizer has already\nestablished may be reassociated. The name suggests a plain lane preserving\nwidening add, which is a different and useful operation that a target may\nwant to expose separately.\n\nRename the optabs and the standard pattern names to reduc_widen_ssum and\nreduc_widen_usum, which puts them alongside the other reduc_* names and\nleaves widen_[us]sum free for a lane preserving pattern. The internal\noptab identifiers become reduc_widen_ssum_optab and reduc_widen_usum_optab\nrather than keeping the reversed reduc_ssum_widen_optab form of the old\nssum_widen_optab and usum_widen_optab, so that the identifier now reads the\nsame way as the pattern name it generates.\n\nThis is a pure rename. No pattern gains or loses a mode, so generated code\nis unchanged.\n\nBootstrapped and tested on aarch64-none-linux-gnu and confirmed that each of\nthe targets affected by the renaming builds.\n\ngcc/ChangeLog:\n\n\t* optabs.def (ssum_widen_optab): Rename to ...\n\t(reduc_widen_ssum_optab): ... this. Rename the pattern from\n\twiden_ssum$a$b3 to reduc_widen_ssum$a$b3.\n\t(usum_widen_optab): Rename to ...\n\t(reduc_widen_usum_optab): ... this. Rename the pattern from\n\twiden_usum$a$b3 to reduc_widen_usum$a$b3.\n\t* optabs-tree.cc (optab_for_tree_code): Update for the renamed\n\toptabs.\n\t* doc/md.texi (widen_ssum@var{n}@var{m}3): Rename to ...\n\t(reduc_widen_ssum@var{n}@var{m}3): ... this.\n\t(widen_usum@var{n}@var{m}3): Rename to ...\n\t(reduc_widen_usum@var{n}@var{m}3): ... this.\n\t* config/aarch64/aarch64-simd.md (widen_ssum\u003cVdblw\u003e\u003cmode\u003e3): Rename\n\tto ...\n\t(reduc_widen_ssum\u003cVdblw\u003e\u003cmode\u003e3): ... this.\n\t(widen_ssum\u003cVwide\u003e\u003cmode\u003e3): Rename to ...\n\t(reduc_widen_ssum\u003cVwide\u003e\u003cmode\u003e3): ... this.\n\t(widen_usum\u003cVdblw\u003e\u003cmode\u003e3): Rename to ...\n\t(reduc_widen_usum\u003cVdblw\u003e\u003cmode\u003e3): ... this.\n\t(widen_usum\u003cVwide\u003e\u003cmode\u003e3): Rename to ...\n\t(reduc_widen_usum\u003cVwide\u003e\u003cmode\u003e3): ... this.\n\t(widen_ssum\u003cmode\u003e\u003cvsi2qi\u003e3): Rename to ...\n\t(reduc_widen_ssum\u003cmode\u003e\u003cvsi2qi\u003e3): ... this.\n\t(widen_usum\u003cmode\u003e\u003cvsi2qi\u003e3): Rename to ...\n\t(reduc_widen_usum\u003cmode\u003e\u003cvsi2qi\u003e3): ... this.\n\t* config/aarch64/aarch64-sve.md (widen_\u003csur\u003esum\u003cmode\u003e\u003cvsi2qi\u003e3):\n\tRename to ...\n\t(reduc_widen_\u003csur\u003esum\u003cmode\u003e\u003cvsi2qi\u003e3): ... this.\n\t* config/aarch64/aarch64-sve2.md (widen_ssum\u003cmode\u003e\u003cVnarrow\u003e3): Rename\n\tto ...\n\t(reduc_widen_ssum\u003cmode\u003e\u003cVnarrow\u003e3): ... this.\n\t(widen_usum\u003cmode\u003e\u003cVnarrow\u003e3): Rename to ...\n\t(reduc_widen_usum\u003cmode\u003e\u003cVnarrow\u003e3): ... this.\n\t* config/arm/neon.md (widen_ssum\u003cv_double_width\u003e\u003cmode\u003e3): Rename\n\tto ...\n\t(reduc_widen_ssum\u003cv_double_width\u003e\u003cmode\u003e3): ... this.\n\t(widen_ssum\u003cV_widen_l\u003e\u003cmode\u003e3): Rename to ...\n\t(reduc_widen_ssum\u003cV_widen_l\u003e\u003cmode\u003e3): ... this.\n\t(widen_usum\u003cv_double_width\u003e\u003cmode\u003e3): Rename to ...\n\t(reduc_widen_usum\u003cv_double_width\u003e\u003cmode\u003e3): ... this.\n\t(widen_usum\u003cV_widen_l\u003e\u003cmode\u003e3): Rename to ...\n\t(reduc_widen_usum\u003cV_widen_l\u003e\u003cmode\u003e3): ... this.\n\t* config/ia64/vect.md (widen_usumv4hiv8qi3): Rename to ...\n\t(reduc_widen_usumv4hiv8qi3): ... this.\n\t(widen_usumv2siv4hi3): Rename to ...\n\t(reduc_widen_usumv2siv4hi3): ... this.\n\t(widen_ssumv4hiv8qi3): Rename to ...\n\t(reduc_widen_ssumv4hiv8qi3): ... this.\n\t(widen_ssumv2siv4hi3): Rename to ...\n\t(reduc_widen_ssumv2siv4hi3): ... this.\n\t* config/rs6000/altivec.md (widen_usumv4si\u003cmode\u003e3): Rename to ...\n\t(reduc_widen_usumv4si\u003cmode\u003e3): ... this.\n\t(widen_ssumv4siv16qi3): Rename to ...\n\t(reduc_widen_ssumv4siv16qi3): ... this.\n\t(widen_ssumv4siv8hi3): Rename to ...\n\t(reduc_widen_ssumv4siv8hi3): ... this.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n" }, { "commit": "adc20f13b60f90c6a55d46fc6be37dfb9f4b86a0", "tree": "cbb5552349ce7e8afe2dcfe4897874114870a423", "parents": [ "9b1c9b6436aad6180192c175554d99f1e38bc7c8" ], "author": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Mon Aug 03 19:54:47 2026 +0200" }, "committer": { "name": "Richard Biener", "email": "rguenth@gcc.gnu.org", "time": "Wed Aug 12 13:17:36 2026 +0200" }, "message": "tree-optimization/126099 - SLP subgraph merging with low/highpart extracts\n\nThe following implements merging of SLP subgraphs that overlap in\ntheir vectors low or highparts or in full vector copies using VEC_PERM\nSLP nodes which know how to perform these extractions, but not more\nin general.\n\nThe operation is to build a reverse mapping of scalar stmt to SLP node\nfor possible extraction starts - without knowing the extraction vector\ntype that\u0027s even lanes of SLP nodes with an even number of lanes. And\nthen for each SLP node lane zero checking whether it\u0027s fully contained\nin one of the candidates with the restrictions implied by\nvectorizable_slp_permutation.\n\nThe motivating testcase is in PR126053 coming from 508.namd_r. The\ntestcases gcc.dg/vect/bb-slp-pr126099-{4,5}.c are cases where schedule\nverification strips one of the graph entries as subgraph merging\notherwise causes SSA verification failures.\n\n\tPR tree-optimization/126099\n\tPR tree-optimization/126053\n\t* tree-vect-slp.cc (vect_cse_gather_part_starts): New function.\n\t(vect_cse_slp_node_parts): Likewise.\n\t(vect_optimize_slp): For BB SLP CSE to low/highparts of\n\tother nodes.\n\n\t* gcc.dg/vect/bb-slp-pr126099-1.c: New testcase.\n\t* gcc.dg/vect/bb-slp-pr126099-2.c: Likewise.\n\t* gcc.dg/vect/bb-slp-pr126099-3.c: Likewise.\n\t* gcc.dg/vect/bb-slp-pr126099-4.c: Likewise.\n\t* gcc.dg/vect/bb-slp-pr126099-5.c: Likewise.\n\t* gcc.dg/vect/costmodel/x86_64/costmodel-pr126053.c: Likewise.\n" }, { "commit": "9b1c9b6436aad6180192c175554d99f1e38bc7c8", "tree": "064055396cd91f5f14b89e89b0a2aa40b94ac0ac", "parents": [ "5e63fb58f84e3ce19cb336710f69094ecbd4b63d" ], "author": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Tue Aug 04 11:20:02 2026 +0200" }, "committer": { "name": "Richard Biener", "email": "rguenth@gcc.gnu.org", "time": "Wed Aug 12 13:17:36 2026 +0200" }, "message": "Verify BB SLP scheduling\n\nThe following adds verification to SLP node scheduling, detecting when\nan invalid schedule is produced (which will result in SSA use before\ndef) and failing BB vectorization in that case. This builds upon\nthe patch computing the schedule and adds verification to the\nfixed root anchors. If an SLP graph entry cannot be scheduled it\nwill be elided.\n\n\t* tree-vectorizer.h (vect_schedule_slp): Adjust prototype.\n\t* tree-vect-slp.cc (vect_slp_analyze_bb_1): When scheduling\n\tfails, fail vectorization.\n\t(vect_schedule_slp_node): Return whether we can schedule\n\tthe node.\n\t(vect_schedule_scc): Likewise.\n\t(vect_schedule_slp): When asked, elide SLP graph entries\n\tthat cannot be scheduled.\n" }, { "commit": "5e63fb58f84e3ce19cb336710f69094ecbd4b63d", "tree": "0555c4321f9f79a54f44b973adb1988936142863", "parents": [ "a3732e7393cead21429e6d70217069fafbc69d61" ], "author": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Wed Jul 15 15:33:31 2026 +0200" }, "committer": { "name": "Richard Biener", "email": "rguenth@gcc.gnu.org", "time": "Wed Aug 12 13:17:36 2026 +0200" }, "message": "tree-optimization/126028 - vector placement and live lane extracts\n\nWe currently conservatively assume vector stmt placement when\ndetermining whether we can place a lane extraction for a live\nscalar value. The following attempts to improve this by\npre-computing an insertion place for all nodes and using that\nto improve live lane extract feasibility computation.\n\nWhile we\u0027d like to re-use such computation for the actual insertion\nthere are issues preventing that such as scalar stmts eventually\ngetting elided and thus iterators invalidated. So the following\nre-computes the scheduling again but at least validates the earlier\nschedule against it.\n\nFor PR126099 I have to turn this into schedule validation, but\nnot as part of this initial work.\n\nThe major pain-point of chosing a gimple * as scheduling anchor\nare that for placement in empty BBs that is NULL (this hits us\nwith region boundaries), a gsi would be able to handle this\ncase. But then, as you can see in the blob that attempts to\nverify the early schedule constraints hold at transform time\nthere\u0027s issues like the scalar stmts vanishing and statements\nbeing inserted. As most viable and ugly option I briefly\nconsidered inserting GIMPLE_NOPs as anchors. Instead of\nvect_schedule_slp_node computing the insertion place this\ncould be also handled (or just overridden?) by vectorizable_*\nwhich sometimes has its own idea where to place.\n\n\tPR tree-optimization/126028\n\t* tree-vectorizer.h (_slp_tree::si): New member.\n\t(vect_schedule_slp): Adjust prototype.\n\t* tree-vect-loop.cc (vect_transform_loop): Adjust.\n\t* tree-vect-slp.cc (_slp_tree::_slp_tree): Initialize si.\n\t(vect_bb_slp_mark_live_stmts): Use vector stmt placement\n\tconstraint computed by pre-scheduling of SLP nodes.\n\t(vect_slp_analyze_bb_1): Pre-schedule SLP nodes before\n\tcomputing live lane extraction points.\n\t(vect_slp_region): Adjust.\n\t(vect_schedule_slp_node): Add parameter indicating to whether\n\twe should perform pre-scehduling or not. Compute the\n\tinsertion place suitable for dominance checks when\n\tpre-scheduling.\n\t(vect_schedule_scc): Adjust.\n\t(vect_schedule_slp): Likewise.\n\n\t* gcc.dg/vect/bb-slp-46.c: Un-XFAIL.\n\t* gcc.dg/vect/bb-slp-pr126053.c: New testcase.\n\t* gcc.dg/vect/costmodel/x86_64/costmodel-pr126028.c: Likewise.\n" }, { "commit": "a3732e7393cead21429e6d70217069fafbc69d61", "tree": "36643fc298a9dc253f3a9bf32042a427f3eaa416", "parents": [ "81b7d7b827252fd93694812ccc751059b2c0d8e4" ], "author": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Wed Aug 12 11:24:01 2026 +0200" }, "committer": { "name": "Richard Biener", "email": "rguenth@gcc.gnu.org", "time": "Wed Aug 12 13:16:31 2026 +0200" }, "message": "Remove dead code from vectorizable_condition\n\nWe no longer have COMPARISON_CLASS_P first operand of COND_EXPRs, not\nfrom patterns either, as the assert in vectorizable_condition shows.\nThe following prunes unreachable code from masked being always true.\n\n\t* tree-vect-stmts.cc (vect_is_simple_cond): Simplify and\n\tinline ...\n\t(vectorizable_condition): ... here. Simplify.\n" }, { "commit": "81b7d7b827252fd93694812ccc751059b2c0d8e4", "tree": "384b419d234ee739d2838ffcad2613effc5d6a59", "parents": [ "a7bdb519ace49050d2c59c78829edfb216afef64" ], "author": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Mon Aug 10 01:15:59 2026 -0700" }, "committer": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Aug 12 12:01:40 2026 +0200" }, "message": "aarch64: accept x8-x15 in aarch64_general_reg\n\nThe peephole2 patterns that fuse a comparison and a subtraction into SUBS\nrequire their destination to satisfy aarch64_general_reg. That predicate\ncompares REGNO_REG_CLASS against GENERAL_REGS, but REGNO_REG_CLASS returns\nthe smallest class holding the register, and since the SME2 support added\nW8_W11_REGS and W12_W15_REGS it does not return GENERAL_REGS for x8-x15.\nThe peepholes therefore stop firing whenever the register allocator puts\nthe difference in one of those eight registers:\n\n (set (reg:CC cc) (compare:CC (reg:DI x2) (reg:DI x5)))\n (set (reg:DI x9) (minus:DI (reg:DI x2) (reg:DI x5)))\n\n -\tcmp\tx2, x5\n +\tsubs\tx9, x2, x5\n\nTest the register number instead. The stack pointer is still rejected,\nwhich is what the predicate was added for.\nBootstrapped and tested on aarch64-none-linux-gnu.\nOk for trunk?\nThanks,\nKyrill\n\ngcc/ChangeLog:\n\n\t* config/aarch64/predicates.md (aarch64_general_reg): Test the\n\tregister number rather than REGNO_REG_CLASS, which reports the\n\tW8_W11_REGS and W12_W15_REGS subclasses for x8-x15.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/rtl/aarch64/subs_general_reg.c: New test.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n" }, { "commit": "a7bdb519ace49050d2c59c78829edfb216afef64", "tree": "a3572fbcc010e864c454e71657bb4ff18288345f", "parents": [ "5d123455af27c526d9aa1e12a47d0177262b0e51" ], "author": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Tue Aug 11 08:11:17 2026 -0700" }, "committer": { "name": "Kyrylo Tkachov", "email": "ktkachov@nvidia.com", "time": "Wed Aug 12 11:36:06 2026 +0200" }, "message": "aarch64: Define __ARM_FEATURE_CSSC ACLE macro\n\nACLE 2025 Q3 specifies the feature test macro __ARM_FEATURE_CSSC, defined\nto 1 when the Common Short Sequence Compression instructions (FEAT_CSSC)\nare available. GCC has generated ABS, CNT, CTZ, SMAX, SMIN, UMAX and\nUMIN for +cssc since GCC 13 but never defined the macro, whereas Clang\nhas defined it since LLVM 21.\n\nDefine it as usual. There are no intrinsics associated with it.\n\nBootstrapped and tested on aarch64-none-linux-gnu.\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define\n\t__ARM_FEATURE_CSSC for TARGET_CSSC.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/pragma_cpp_predefs_4.c: Add __ARM_FEATURE_CSSC\n\ttests.\n\nSigned-off-by: Kyrylo Tkachov \u003cktkachov@nvidia.com\u003e\n" }, { "commit": "5d123455af27c526d9aa1e12a47d0177262b0e51", "tree": "5907378ba88bc7b014c274e222284a4ba471907a", "parents": [ "f6a1e69999d7b614cbcedff6ecaa01b713f31266" ], "author": { "name": "Richard Biener", "email": "rguenther@suse.de", "time": "Wed Aug 12 08:59:18 2026 +0200" }, "committer": { "name": "Richard Biener", "email": "rguenth@gcc.gnu.org", "time": "Wed Aug 12 10:31:49 2026 +0200" }, "message": "tree-optimization/126789 - MMX and SSE mask interaction with AVX512\n\nThe following makes the vectorizer deal with the fact that the x86\nbackend can have a set of integer mode masks and a set of integer\nvector mode masks depending on active ISAs. To convert between\nboth representations we have to use vcond_mask for integer mode\nto integer vector mode. For the case of V2SImode the backend\ncurrently misses patterns which the following adds. Now, when\ndoing BB vectorization the vectorizer pattern recognition cannot\nknow that we\u0027ll use V2SImode with a vector integer mask mode but\nit guesses V16SImode which would use DImode. So we cannot arrange\nfor the mask representation conversion during pattern recognition,\nbut it\u0027s easy to handle VECTOR_BOOLEAN_TYPE_P conversions with\nvcond_mask as option in vectorizable_conversion, so that\u0027s what the\npatch does.\n\nI don\u0027t have a testcase for the reverse which would need to use\nvcmp[_eq] to convert from integer vector mode to integer mode mask,\nso I\u0027m not implementing that with this patch.\n\n\tPR tree-optimization/126789\n\t* config/i386/mmx.md (mmxxmmmode): Add V2SF and V2SI.\n\t(mmxxmmmodelower): Likewise.\n\t(vcond_mask_\u003cmode\u003eqi): New expander for V2SF and V2SI.\n\t* tree-vect-stmts.cc (vectorizable_conversion): Handle\n\tconversion via VEC_COND_EXPR.\n\t(supportable_indirect_convert_operation): For mask vector\n\tconversions to vector integer mode try using a VEC_COND_EXPR.\n\n\t* gcc.target/i386/vect-pr126789-2.c: New testcase.\n" }, { "commit": "f6a1e69999d7b614cbcedff6ecaa01b713f31266", "tree": "118695d8174135f4b4362480bc64e25bc8ddc33c", "parents": [ "218575554420ded75052e56d5a89cd23522f20a7" ], "author": { "name": "Jørgen Kvalsvik", "email": "j@lambda.is", "time": "Tue Sep 30 11:23:56 2025 +0200" }, "committer": { "name": "Jørgen Kvalsvik", "email": "j@lambda.is", "time": "Wed Aug 12 10:19:29 2026 +0200" }, "message": "Add attribute and pragma for coverage suppression\n\nAdd support for suppressing coverage, either at the function level\nwith the attribute [[gnu::suppress_coverage]] or at the line level\nwith #pragma GCC suppress_coverage begin/end. This is quite useful\nfor things like unreachable states which would score worse on coverage\ndespite being better code, or when a specific functions should be\nomitted from coverage.\n\nA motivating example from the wild are contracts in debug\nbuilds. Let\u0027s assume we have a precondition assert macro:\n\n #define REQUIRE(pred) assert (((void)\"Precondition violated\", pred))\n\n int div (int x, int y)\n {\n REQUIRE (y !\u003d 0);\n return x / y;\n }\n\nThe REQUIRE/assert introduces a branch in code that is otherwise a\nstraight line, and if the function is never called with y \u003d 0 (which\nis undefined), the assert-failure branch will not be covered, which\npollutes the coverage report. GCC and gcov can already filter out on\nthe function and file level (e.g. -fprofile-filter-files\u003d\u003cregex\u003e), but\nthat is not sufficient for this use case. The suppress_coverage\nattribute and pragma high precision tool for very specific bits of code\nthat shouldn\u0027t be counted towards coverage.\n\nWe can change the REQUIRE macro to this to make the problem\ngo away:\n\n #define REQUIRE(pred) do { \\\n _Pragma (\"GCC suppress_coverage begin\"); \\\n assert (((void)\"Precondition violated\", pred)); \\\n _Pragma (\"GCC suppress_coverage end\"); \\\n } while (0)\n\n--\n\nDEMO\n\ngcc div.c -o div --coverage \u0026\u0026 gcov -fbc div\n\nWithout coverage suppression. The fallthrough branch is taken 0 times,\nand we have 50% branch coverage.\n\nFunction \u0027div\u0027\nLines executed:100.00% of 3\nBranches executed:100.00% of 2\nTaken at least once:50.00% of 2\nNo calls\n -: 0:Source:div.c\n -: 0:Graph:div.gcno\n -: 0:Data:div.gcda\n -: 0:Runs:1\n -: 1:#include \u003cassert.h\u003e\n -: 2:\n -: 3:#define REQUIRE(pred, msg) \\\n -: 4: assert (((void)msg, pred))\n -: 5:\nfunction div called 1 returned 100% blocks executed 75%\n 1: 6:double div (double x, double y)\n -: 7:{\n -: 8: /* gcov reports that this function has no branches. */\n 1*: 9: REQUIRE (y !\u003d 0, \"division by zero\");\nbranch 0 taken 0 (fallthrough)\nbranch 1 taken 1\ncall 2 never executed\n 1: 10: return x / y;\n -: 11:}\n -: 12:\nfunction main called 1 returned 100% blocks executed 100%\n 1: 13:int main() {\n 1: 14: return div(0, 5);\ncall 0 returned 1\n -: 15:}\n\nThe branch is effectively gone with suppresion:\n\nFunction \u0027div\u0027\nLines executed:100.00% of 2 (1 of 3 suppressed)\nBranches executed:0.00% of 0 (2 of 2 suppressed)\nTaken at least once:0.00% of 0\nCalls executed:0.00% of 0 (1 of 1 suppressed)\n -: 0:Source:div.c\n -: 0:Graph:div.gcno\n -: 0:Data:div.gcda\n -: 0:Runs:1\n -: 1:#include \u003cassert.h\u003e\n -: 2:\n -: 3:#define REQUIRE(pred, msg) do { \\\n -: 4: _Pragma (\"GCC suppress_coverage begin\"); \\\n -: 5: assert (((void)msg, pred)); \\\n -: 6: _Pragma (\"GCC suppress_coverage end\"); \\\n -: 7:} while (0)\n -: 8:\nfunction div called 1 returned 100% blocks executed 80%\n 1: 9:double div (double x, double y)\n -: 10:{\n -: 11: /* gcov reports that this function has no branches. */\n #: 12: REQUIRE (y !\u003d 0, \"division by zero\");\n 1: 13: return x / y;\n -: 14:}\n -: 15:\nfunction main called 1 returned 100% blocks executed 100%\n 1: 16:int main() {\n 1: 17: return div(0, 5);\ncall 0 returned 1\n -: 18:}\n\n--\n\nIMPLEMENTATION DETAILS\n\nWe record the expanded source location of the pragma and consult them\nduring tree-cfg construction. If a statement\u0027s location is anchored\nbetween a begin/end, we record the basic block suppressed in the new\nSUPPRESS record. We split a block when only parts of it have coverage\nsuppressed, and take suppression into account when we consider merging\nblocks, generally prohibiting merges with different suppression flags.\n\nThis feature is designed so that it does not actually disable the arc\nprofiling instrumentation itself as we don\u0027t want this attribute\nmessing with profile-guided optimization or other uses. Instead, we\ndo the actual suppression in gcov. However, when the whole function\nis within a begin/end, or when annotated with\n[[gnu::suppress_coverage]], we can disable MC/DC and prime path\ncoverage as those are only used for coverage, not pgo. This just\nworks; we just omit the record, and gcov is none the wiser.\n\n--\n\nGCOV\n\nThe coverage instrumentation is not actually changed in any meaningful\nway, suppressing coverage is about interpretation. Rather than changing\nthe instrumentation, we add a new SUPPRESS record with metadata which\ntells gcov which blocks should be blacklisted from the coverage\nreport. When gcov prints its report it checks blocks against the\nSUPPRESS record, and by extension arc, condition, and path, against the\nblacklist and decides whether or not to include it.\n\nPrime paths turned out to be tricky. If we suppress out a subsequence we\nwant to unify the paths that used to differ but now don\u0027t care about\nthe path through the suppressed subgraph, and either may have been\ncovered.\n\nFunction-level suppressions are implemented by GCC recording the ENTRY\nblock (0) as suppressed. This block cannot be marked by user programs\nanyway so we get to claim it, and it makes sense that an ignored entry\nblock implies the whole function.\n\n--\n\ngcc/c-family/ChangeLog:\n\n\t* c-attribs.cc (handle_suppress_coverage_attribute): New\n\tfunction.\n\t* c-pragma.cc (handle_pragma_suppress_coverage): New function.\n\t(init_pragma): Register pragma GCC suppress_coverage.\n\t* c-pragma.h (suppress_coverage_begin): New forward declaration.\n\t(suppress_coverage_end): Ditto.\n\ngcc/ChangeLog:\n\n\t* cfg-flags.def (COVERAGE_SUPPRESSED): New flag.\n\t* doc/extend.texi: Add sections on suppress_coverage.\n\t* doc/gcov.texi: Add sections on suppress_coverage.\n\t* gcov-dump.cc (tag_suppress): New function.\n\t* gcov-io.h (GCOV_TAG_SUPPRESS): New.\n\t(GCOV_TAG_SUPPRESS_LENGTH): New.\n\t(GCOV_TAG_SUPPRESS_NUM): New.\n\t* gcov.cc (struct arc_info): Add field suppressed.\n\t(block_info::block_info): Initialize suppressed.\n\t(line_info::line_info): Initialize suppressed.\n\t(struct coverage_info): Add fields lines_suppressed,\n\t(struct path_info): Add fields residual_paths,\n\tresidual_covered.\n\t(executed_summary): Add suppressed argument.\n\t(tombstone_p): New function.\n\t(remove_tombstones): New function.\n\t(tombstone_subsequence_p): New function.\n\t(subsumed_by_any_p): New function.\n\t(path_info::suppress_blocks): New function.\n\t(path_info::get_paths): New function.\n\t(path_info::count): New function.\n\t(path_info::suppressed_count): New function.\n\t(path_info::suppressed_p): New function.\n\t(find_arc): Return NULL if arc cannot be found.\n\t(main): Pass total_suppressed to executed_summary.\n\t(output_intermediate_json_line): Skip suppressed.\n\t(json_set_prime_path_coverage): Include suppressed counts.\n\t(output_json_intermediate_file): Likewise.\n\t(process_all_functions): Record block, arc suppressed status.\n\t(generate_results): Count total suppressed.\n\t(read_graph_file): Read SUPPRESS tag.\n\t(add_branch_counts): Count suppressed.\n\t(add_condition_counts): Likewise.\n\t(add_path_counts): Likewise.\n\t(function_summary): Print info on suppressed blocks.\n\t(file_summary): Count suppressed.\n\t(add_line_counts): Likewise.\n\t(accumulate_line_info): Likewise.\n\t(accumulate_line_counts): Likewise.\n\t(output_conditions): Skip suppressed.\n\t(output_branch_count): Likewise.\n\t(print_prime_path_lines): Annotate suppressed arcs.\n\t(print_prime_path_source): Likewise, and widen the annotation\n\tcolumn.\n\t(output_path_coverage): Print info on suppressed paths.\n\t(output_line_beginning): Prefix suppressed lines with \u0027#\u0027.\n\t(output_line_details): Pass suppressed.\n\t(output_lines): Likewise.\n\t* profile.cc (suppress_coverage): New function.\n\t(suppress_coverage_unset): New function.\n\t(coverage_suppressed_p): New function.\n\t(any_block_coverage_suppressed_p): New function.\n\t(suppress_coverage_begin): New function.\n\t(suppress_coverage_end): New function.\n\t(in_pragma_suppress_coverage_p): New function.\n\t(location_in_pragma_suppress_coverage_p): New function.\n\t(fn_in_pragma_suppress_coverage_p): New function.\n\t(branch_prob): Write SUPPRESS record, skip MC/DC and path\n\tcoverage when the entire function is suppressed.\n\t* profile.h (in_pragma_suppress_coverage_p): New forward\n\tdeclaration.\n\t(location_in_pragma_suppress_coverage_p): Ditto.\n\t(coverage_suppressd_p): Ditto.\n\t(suppress_coverage): Ditto.\n\t(suppress_coverage_unset): Ditto.\n\t* tree-cfg.cc (gimple_empty_block_p): New forward declaration.\n\t(make_blocks_1): Set coverage-suppresesed on blocks.\n\t(make_blocks): Sometimes insert NOP to help coverage\n\tsuppression on blocks.\n\t(gimple_can_merge_blocks_p): Don\u0027t merge coverage-suppressed\n\tblock with non-suppressed blocks.\n\t(gimple_merge_blocks): Likewise.\n\t(gimple_split_edge): Propagate coverage-suppressed on block\n\tsplits.\n\t(gimple_split_block): Likewise.\n\t(gimple_duplicate_bb): Likewise.\n\t(insert_cond_bb): Likewise.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/gcov/gcov-24.C: New test.\n\t* g++.dg/gcov/gcov-25.C: New test.\n\t* g++.dg/gcov/gcov-26.C: New test.\n\t* g++.dg/gcov/gcov-27.C: New test.\n\t* gcc.dg/pragma-suppress-coverage.c: New test.\n\t* gcc.misc-tests/gcov-37.c: New test.\n\t* gcc.misc-tests/gcov-38.c: New test.\n\t* gcc.misc-tests/gcov-39.c: New test.\n\t* gcc.misc-tests/gcov-40.c: New test.\n\t* gcc.misc-tests/gcov-41.c: New test.\n\t* gcc.misc-tests/gcov-42.c: New test.\n\t* gcc.misc-tests/gcov-42.h: New test.\n" }, { "commit": "218575554420ded75052e56d5a89cd23522f20a7", "tree": "b2227331f58162875dc2f78cfaa2856b0cb8458a", "parents": [ "89c1412dfc26d141a6d8732b269c3e30eff44613" ], "author": { "name": "Aldy Hernandez", "email": "aldy@quesejoda.com", "time": "Tue Aug 11 08:36:36 2026 +0000" }, "committer": { "name": "Aldy Hernandez", "email": "aldy@quesejoda.com", "time": "Wed Aug 12 10:06:47 2026 +0200" }, "message": "Thread paths ending in a computed goto\n\nThe backward threader only handles paths ending in a GIMPLE_COND or\nGIMPLE_SWITCH, even though the profitability code and the generic\ncopier already accounts for GIMPLE_GOTO. When we rewrote the\nbackwards threader, the GIMPLE_GOTO handling was silently dropped\nbecause (a) ranger couldn\u0027t handle symbolics (b) DOM was picking our\nslack. Now with DOM removal in our sights, we need to handle computed\ngotos. This has been made trivial, by the recent work in prange\nproviding points-to info.\n\nNote that a destination occurring in an abnormal PHI (when the goto\nblock is itself one of the goto\u0027s targets) is still not handled. I\u0027ll\nbe working on abnormal edge handling as a follow-up.\n\nTested on ppc64le Linux.\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/126103\n\t* tree-ssa-threadbackward.cc (class back_threader): Add\n\tfind_taken_edge_goto.\n\t(back_threader::find_taken_edge): Handle GIMPLE_GOTO.\n\t(back_threader::find_taken_edge_goto): New.\n\t(back_threader::maybe_thread_block): Handle GIMPLE_GOTO.\n\ngcc/testsuite/ChangeLog:\n\n\tPR tree-optimization/126103\n\t* gcc.dg/pr89737.c: Add -fno-thread-jumps.\n\t* gcc.dg/tree-ssa/backthread-computed-goto-1.c: New test.\n\t* gcc.dg/tree-ssa/backthread-computed-goto-3.c: New test.\n" }, { "commit": "89c1412dfc26d141a6d8732b269c3e30eff44613", "tree": "fa3e6ab99b5a68a5ac8f5c132f5183e5e1754ff3", "parents": [ "67c9a2c1c7ed4414151acef4a8e336c751959225" ], "author": { "name": "Jakub Jelinek", "email": "jakub@redhat.com", "time": "Wed Aug 12 10:02:37 2026 +0200" }, "committer": { "name": "Jakub Jelinek", "email": "jakub@redhat.com", "time": "Wed Aug 12 10:02:37 2026 +0200" }, "message": "c++: Change alignof (decltype (^^::)) from 1 to alignof (void *)\n\nWe IMHO incorrectly leave TYPE_ALIGN of std::meta::info unset, so alignof on\nit is 1. We should change that to the same as decltype (nullptr) and\nvoid *.\nAs C++26 is heavily experimental, this is changed unconditionally, without\n-fabi-version\u003d checks, and only for 17, not for 16.x.\n\n2026-08-12 Jakub Jelinek \u003cjakub@redhat.com\u003e\n\n\t* reflect.cc (init_reflection): Also initialize TYPE_UNSIGNED,\n\tTYPE_PRECISION, TYPE_MODE and TYPE_ALIGN of meta_info_type_node.\n\n\t* g++.dg/reflect/info1.C: New test.\n\nReviewed-by: Jason Merrill \u003cjason@redhat.com\u003e\n" }, { "commit": "67c9a2c1c7ed4414151acef4a8e336c751959225", "tree": "12902a672ca3ab35e6a50f48dc1ebc32f583cefc", "parents": [ "475e9efffaf8de781d7e17b687faf1807e104b01" ], "author": { "name": "Tamar Christina", "email": "tamar.christina@arm.com", "time": "Wed Aug 12 07:57:39 2026 +0100" }, "committer": { "name": "Tamar Christina", "email": "tamar.christina@arm.com", "time": "Wed Aug 12 07:57:39 2026 +0100" }, "message": "vect: fix virtual PHI after header rewrite [PR126778]\n\nThe loop header rewrite in vect_set_loop_condition_partial_vectors runs after\nearly break store movement and so it has to update any virtual operands on the\nexit edge.\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/126778\n\t* tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge): Move it.\n\t(vect_set_loop_condition_partial_vectors): Use it to update edge.\n\ngcc/testsuite/ChangeLog:\n\n\tPR tree-optimization/126778\n\t* gcc.dg/vect/vect-early-break_145-pr126778_1.c: New test.\n\t* gcc.dg/vect/vect-early-break_145-pr126778_2.c: New test.\n" } ], "next": "475e9efffaf8de781d7e17b687faf1807e104b01" }