| [^:]*: Assembler messages: |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Error: bad type in SIMD instruction -- `vaddlv.i32 r0,r1,q0' |
| [^:]*:14: Error: bad type in SIMD instruction -- `vaddlv.f32 r0,r1,q0' |
| [^:]*:15: Error: bad type in SIMD instruction -- `vaddlv.s8 r0,r1,q0' |
| [^:]*:16: Error: bad type in SIMD instruction -- `vaddlv.s16 r0,r1,q0' |
| [^:]*:17: Error: bad type in SIMD instruction -- `vaddlv.s64 r0,r1,q0' |
| [^:]*:18: Error: bad type in SIMD instruction -- `vaddlv.u8 r0,r1,q0' |
| [^:]*:19: Error: bad type in SIMD instruction -- `vaddlv.u16 r0,r1,q0' |
| [^:]*:20: Error: bad type in SIMD instruction -- `vaddlv.u64 r0,r1,q0' |
| [^:]*:21: Error: bad type in SIMD instruction -- `vaddlva.i32 r0,r1,q0' |
| [^:]*:22: Error: bad type in SIMD instruction -- `vaddlva.f32 r0,r1,q0' |
| [^:]*:23: Error: bad type in SIMD instruction -- `vaddlva.s8 r0,r1,q0' |
| [^:]*:24: Error: bad type in SIMD instruction -- `vaddlva.s16 r0,r1,q0' |
| [^:]*:25: Error: bad type in SIMD instruction -- `vaddlva.s64 r0,r1,q0' |
| [^:]*:26: Error: bad type in SIMD instruction -- `vaddlva.u8 r0,r1,q0' |
| [^:]*:27: Error: bad type in SIMD instruction -- `vaddlva.u16 r0,r1,q0' |
| [^:]*:28: Error: bad type in SIMD instruction -- `vaddlva.u64 r0,r1,q0' |
| [^:]*:29: Error: Odd register not allowed here -- `vaddlv.s32 r1,r3,q0' |
| [^:]*:30: Error: Even register not allowed here -- `vaddlva.s32 r0,r2,q0' |
| [^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:33: Error: syntax error -- `vaddlveq.s32 r0,r1,q0' |
| [^:]*:34: Error: syntax error -- `vaddlveq.s32 r0,r1,q0' |
| [^:]*:36: Error: syntax error -- `vaddlveq.s32 r0,r1,q0' |
| [^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vaddlvt.s32 r0,r1,q0' |
| [^:]*:39: Error: instruction missing MVE vector predication code -- `vaddlv.s32 r0,r1,q0' |
| [^:]*:41: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0' |
| [^:]*:42: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0' |
| [^:]*:44: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0' |
| [^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vaddlvat.s32 r0,r1,q0' |
| [^:]*:47: Error: instruction missing MVE vector predication code -- `vaddlva.s32 r0,r1,q0' |
