| [^:]*: Assembler messages: |
| [^:]*:10: Error: bad type in SIMD instruction -- `vmla.f16 q0,q1,r2' |
| [^:]*:11: Error: bad type in SIMD instruction -- `vmla.s64 q0,q1,r2' |
| [^:]*:12: Error: selected FPU does not support instruction -- `vmla.s32 q0,q1,q2' |
| [^:]*:13: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:17: Error: syntax error -- `vmlaeq.u16 q0,q1,r2' |
| [^:]*:18: Error: syntax error -- `vmlaeq.u16 q0,q1,r2' |
| [^:]*:20: Error: syntax error -- `vmlaeq.u16 q0,q1,r2' |
| [^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmlat.u16 q0,q1,r2' |
| [^:]*:23: Error: instruction missing MVE vector predication code -- `vmla.u16 q0,q1,r2' |
