| [^:]*: Assembler messages: |
| [^:]*:10: Error: Odd register not allowed here -- `vmlsdav.s16 r1,q1,q2' |
| [^:]*:11: Error: bad type in SIMD instruction -- `vmlsdav.u16 r0,q1,q2' |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:17: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2' |
| [^:]*:18: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2' |
| [^:]*:20: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2' |
| [^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavt.s16 r0,q1,q2' |
| [^:]*:23: Error: instruction missing MVE vector predication code -- `vmlsdav.s16 r0,q1,q2' |
| [^:]*:25: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2' |
| [^:]*:26: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2' |
| [^:]*:28: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2' |
| [^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavat.s16 r0,q1,q2' |
| [^:]*:31: Error: instruction missing MVE vector predication code -- `vmlsdava.s16 r0,q1,q2' |
| [^:]*:33: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2' |
| [^:]*:34: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2' |
| [^:]*:36: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2' |
| [^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavxt.s16 r0,q1,q2' |
| [^:]*:39: Error: instruction missing MVE vector predication code -- `vmlsdavx.s16 r0,q1,q2' |
| [^:]*:41: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2' |
| [^:]*:42: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2' |
| [^:]*:44: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2' |
| [^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavaxt.s16 r0,q1,q2' |
| [^:]*:47: Error: instruction missing MVE vector predication code -- `vmlsdavax.s16 r0,q1,q2' |