| [^:]*: Assembler messages: |
| [^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:11: Error: bad type in SIMD instruction -- `vmlsldav.u16 r0,r1,q1,q2' |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:16: Error: bad type in SIMD instruction -- `vmlsldav.s64 r0,r1,q1,q2' |
| [^:]*:17: Error: bad type in SIMD instruction -- `vmlsldav.f32 r0,r1,q1,q2' |
| [^:]*:18: Error: bad type in SIMD instruction -- `vmlsldav.s8 r0,r1,q1,q2' |
| [^:]*:19: Error: ARM register expected -- `vmlsldav.s16 r0,q1,q2' |
| [^:]*:20: Error: bad type in SIMD instruction -- `vmlsldava.s64 r0,r1,q1,q2' |
| [^:]*:21: Error: bad type in SIMD instruction -- `vmlsldava.f32 r0,r1,q1,q2' |
| [^:]*:22: Error: bad type in SIMD instruction -- `vmlsldava.s8 r0,r1,q1,q2' |
| [^:]*:23: Error: ARM register expected -- `vmlsldava.s16 r0,q1,q2' |
| [^:]*:24: Error: bad type in SIMD instruction -- `vmlsldavx.s64 r0,r1,q1,q2' |
| [^:]*:25: Error: bad type in SIMD instruction -- `vmlsldavx.f32 r0,r1,q1,q2' |
| [^:]*:26: Error: bad type in SIMD instruction -- `vmlsldavx.s8 r0,r1,q1,q2' |
| [^:]*:27: Error: ARM register expected -- `vmlsldavx.s16 r0,q1,q2' |
| [^:]*:28: Error: bad type in SIMD instruction -- `vmlsldavax.s64 r0,r1,q1,q2' |
| [^:]*:29: Error: bad type in SIMD instruction -- `vmlsldavax.f32 r0,r1,q1,q2' |
| [^:]*:30: Error: bad type in SIMD instruction -- `vmlsldavax.s8 r0,r1,q1,q2' |
| [^:]*:31: Error: ARM register expected -- `vmlsldavax.s16 r0,q1,q2' |
| [^:]*:33: Error: syntax error -- `vmlsldaveq.s16 r0,r1,q1,q2' |
| [^:]*:34: Error: syntax error -- `vmlsldaveq.s16 r0,r1,q1,q2' |
| [^:]*:35: Error: syntax error -- `vmlsldaveq.s16 r0,r1,q1,q2' |
| [^:]*:36: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsldavt.s16 r0,r1,q1,q2' |
| [^:]*:38: Error: instruction missing MVE vector predication code -- `vmlsldav.s16 r0,r1,q1,q2' |
| [^:]*:40: Error: syntax error -- `vmlsldavaeq.s16 r0,r1,q1,q2' |
| [^:]*:41: Error: syntax error -- `vmlsldavaeq.s16 r0,r1,q1,q2' |
| [^:]*:42: Error: syntax error -- `vmlsldavaeq.s16 r0,r1,q1,q2' |
| [^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsldavat.s16 r0,r1,q1,q2' |
| [^:]*:45: Error: instruction missing MVE vector predication code -- `vmlsldava.s16 r0,r1,q1,q2' |
| [^:]*:47: Error: syntax error -- `vmlsldavxeq.s16 r0,r1,q1,q2' |
| [^:]*:48: Error: syntax error -- `vmlsldavxeq.s16 r0,r1,q1,q2' |
| [^:]*:49: Error: syntax error -- `vmlsldavxeq.s16 r0,r1,q1,q2' |
| [^:]*:50: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsldavxt.s16 r0,r1,q1,q2' |
| [^:]*:52: Error: instruction missing MVE vector predication code -- `vmlsldavx.s16 r0,r1,q1,q2' |
| [^:]*:54: Error: syntax error -- `vmlsldavaxeq.s16 r0,r1,q1,q2' |
| [^:]*:55: Error: syntax error -- `vmlsldavaxeq.s16 r0,r1,q1,q2' |
| [^:]*:56: Error: syntax error -- `vmlsldavaxeq.s16 r0,r1,q1,q2' |
| [^:]*:57: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsldavaxt.s16 r0,r1,q1,q2' |
| [^:]*:59: Error: instruction missing MVE vector predication code -- `vmlsldavax.s16 r0,r1,q1,q2' |