| [^:]*: Assembler messages: |
| [^:]*:10: Error: bad type in SIMD instruction -- `vqdmullt.s8 q0,q1,q2' |
| [^:]*:11: Error: bad type in SIMD instruction -- `vqdmullt.u8 q0,q1,q2' |
| [^:]*:12: Error: bad type in SIMD instruction -- `vqdmullt.i16 q0,q1,q2' |
| [^:]*:13: Error: bad type in SIMD instruction -- `vqdmullt.s64 q0,q1,q2' |
| [^:]*:14: Error: bad type in SIMD instruction -- `vqdmullb.s8 q0,q1,q2' |
| [^:]*:15: Error: bad type in SIMD instruction -- `vqdmullb.u8 q0,q1,q2' |
| [^:]*:16: Error: bad type in SIMD instruction -- `vqdmullb.i16 q0,q1,q2' |
| [^:]*:17: Error: bad type in SIMD instruction -- `vqdmullb.s64 q0,q1,q2' |
| [^:]*:18: Error: bad type in SIMD instruction -- `vqdmullt.s8 q0,q1,r2' |
| [^:]*:19: Error: bad type in SIMD instruction -- `vqdmullt.u8 q0,q1,r2' |
| [^:]*:20: Error: bad type in SIMD instruction -- `vqdmullt.i16 q0,q1,r2' |
| [^:]*:21: Error: bad type in SIMD instruction -- `vqdmullt.s64 q0,q1,r2' |
| [^:]*:22: Error: bad type in SIMD instruction -- `vqdmullb.s8 q0,q1,r2' |
| [^:]*:23: Error: bad type in SIMD instruction -- `vqdmullb.u8 q0,q1,r2' |
| [^:]*:24: Error: bad type in SIMD instruction -- `vqdmullb.i16 q0,q1,r2' |
| [^:]*:25: Error: bad type in SIMD instruction -- `vqdmullb.s64 q0,q1,r2' |
| [^:]*:26: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:27: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:28: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:29: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:30: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:31: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:32: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:33: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:34: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:41: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2' |
| [^:]*:42: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2' |
| [^:]*:44: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2' |
| [^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmulltt.s32 q0,q1,q2' |
| [^:]*:47: Error: instruction missing MVE vector predication code -- `vqdmullt.s32 q0,q1,q2' |
| [^:]*:49: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2' |
| [^:]*:50: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2' |
| [^:]*:52: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2' |
| [^:]*:53: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmullbt.s32 q0,q1,q2' |
| [^:]*:55: Error: instruction missing MVE vector predication code -- `vqdmullb.s32 q0,q1,q2' |