gas/testsuite/gas/arm/mve-vqshl-bad.l

[^:]*: Assembler messages:
[^:]*:10: Error: bad type in SIMD instruction -- `vqshl.s64 q0,q0,#0'
[^:]*:11: Error: bad type in SIMD instruction -- `vqshl.i32 q0,q0,#0'
[^:]*:12: Error: immediate out of range for shift -- `vqshl.s8 q0,q1,#8'
[^:]*:13: Error: immediate out of range for shift -- `vqshl.u16 q0,q1,#16'
[^:]*:14: Error: immediate out of range for shift -- `vqshl.s32 q0,q1,#32'
[^:]*:15: Error: bad type in SIMD instruction -- `vqshl.s64 q0,r1'
[^:]*:16: Error: bad type in SIMD instruction -- `vqshl.i16 q0,r1'
[^:]*:17: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:18: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:19: Error: bad type in SIMD instruction -- `vqshl.s64 q0,q1,q2'
[^:]*:20: Error: bad type in SIMD instruction -- `vqshl.i32 q0,q1,q2'
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:25: Error: syntax error -- `vqshleq.s16 q0,q1,#0'
[^:]*:26: Error: syntax error -- `vqshleq.s16 q0,q1,#0'
[^:]*:28: Error: syntax error -- `vqshleq.s16 q0,q1,#0'
[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vqshlt.s16 q0,q1,#0'
[^:]*:31: Error: instruction missing MVE vector predication code -- `vqshl.s16 q0,q1,#0'
[^:]*:33: Error: syntax error -- `vqshleq.s16 q0,r1'
[^:]*:34: Error: syntax error -- `vqshleq.s16 q0,r1'
[^:]*:36: Error: syntax error -- `vqshleq.s16 q0,r1'
[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vqshlt.s16 q0,r1'
[^:]*:39: Error: instruction missing MVE vector predication code -- `vqshl.s16 q0,r1'
[^:]*:41: Error: syntax error -- `vqshleq.s16 q0,q1,q2'
[^:]*:42: Error: syntax error -- `vqshleq.s16 q0,q1,q2'
[^:]*:44: Error: syntax error -- `vqshleq.s16 q0,q1,q2'
[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vqshlt.s16 q0,q1,q2'
[^:]*:47: Error: instruction missing MVE vector predication code -- `vqshl.s16 q0,q1,q2'